Mamidala Jagadesh Kumar

Electrical and Electronic Engineering · 2004–2016

A researcher in the Science corpus: 10 papers; trusts 17 researchers and is trusted by 9 researchers here, as inferred from the citation graph.

Subfields

• Electrical and Electronic Engineering — 50 citations into it; #3,337 of 16,539 by trust here, #7,892 by citations
• Biomedical Engineering — 13 citations into it

Whom Mamidala Jagadesh Kumar trusts overall

Their strongest outbound trust, strongest first, inferred from their citations.

1. K. Boucart
2. Adrian M. Ionescu
3. Anurag Chaudhry
4. D. Abdi
5. M. Jagadesh Kumar
6. Alan C. Seabaugh
7. V. Nagavarapu
8. Y. Qiu
9. S. Janardhanan
10. Ritesh Jhaveri

Who trusts Mamidala Jagadesh Kumar overall

1. Anurag Chaudhry
2. Shubham Sahay
3. Sneh Saurabh
4. J. Madan
5. D. Abdi
6. Sanjay Kumar
7. Ratul Kumar Baruah
8. G. Reddy
9. Rishu Chaujar

Papers from Mamidala Jagadesh Kumar's perspective

Ordered by how strongly the researchers Mamidala Jagadesh Kumar trusts endorse each paper. Same corpus, a different order for every researcher.

1. Double-Gate Tunnel FET With High-$\kappa$ Gate Dielectric (IEEE Transactions on Electron Devices)
2. Low-subthreshold-swing tunnel transistors (IEEE Electron Device Letters)
3. The Charge Plasma P-N Diode (IEEE Electron Device Letters)
4. Length scaling of the Double Gate Tunnel FET with a high-K gate dielectric
5. The Tunnel Source (PNPN) n-MOSFET: A Novel High Performance Transistor (IEEE Transactions on Electron Devices)
6. Double-Gate Strained-Ge Heterostructure Tunneling FET (TFET) With record high drive currents and ≪60mV/dec subthreshold slope (2008 IEEE International Electron Devices Meeting)
7. Effect of Pocket Doping and Annealing Schemes on the Source-Pocket Tunnel Field-Effect Transistor (IEEE Transactions on Electron Devices)
8. Steep Subthreshold Slope n- and p-Type Tunnel-FET Devices for Low-Power and Energy-Efficient Digital Circuits (IEEE Transactions on Electron Devices)
9. Complementary Silicon-Based Heterostructure Tunnel-FETs With High Tunnel Rates (IEEE Electron Device Letters)
10. Low-Voltage Tunnel Transistors for Beyond CMOS Logic (Proceedings of the IEEE)

Their papers

• Novel Attributes of a Dual Material Gate Nanoscale Tunnel Field-Effect Transistor (2011) — 430 citations
• Controlling short-channel effects in deep-submicron SOI MOSFETs for improved reliability: a review (2004) — 460 citations
• Investigation of the novel attributes of a fully depleted dual-material gate SOI MOSFET (2004) — 135 citations
• Controlling Ambipolar Current in Tunneling FETs Using Overlapping Gate-on-Drain (2014) — 282 citations
• In-Built N+ Pocket p-n-p-n Tunnel Field-Effect Transistor (2014) — 138 citations
• Dielectric-Modulated Impact-Ionization MOS Transistor as a Label-Free Biosensor (2013) — 137 citations
• Two-dimensional analytical modeling of fully depleted DMG SOI MOSFET and evidence for diminished SCEs (2004) — 272 citations
• Fundamentals of Tunnel Field-Effect Transistors (2016) — 154 citations
• Controlling the Drain Side Tunneling Width to Reduce Ambipolar Current in Tunnel FETs Using Heterodielectric BOX (2015) — 135 citations
• Bipolar Charge-Plasma Transistor: A Novel Three Terminal Device (2012) — 214 citations