Ritesh Jhaveri
Electrical and Electronic Engineering · 2005–2014
A researcher in the Science corpus: 4 papers; trusts 2 researchers and is trusted by 7 researchers here, as inferred from the citation graph.
Subfields
- Electrical and Electronic Engineering — 22 citations into it; #4,887 of 16,539 by trust here, #7,520 by citations
Whom Ritesh Jhaveri trusts overall
Their strongest outbound trust, strongest first, inferred from their citations.
Who trusts Ritesh Jhaveri overall
- Rakhi Narang
- Y. Qiu
- Bahram Jalali
- D. Abdi
- Manoj Saxena
- Mamidala Jagadesh Kumar
- Runsheng Wang
- Qianqian Huang
Papers from Ritesh Jhaveri's perspective
Ordered by how strongly the researchers Ritesh Jhaveri trusts endorse each paper. Same corpus, a different order for every researcher.
- Lateral interband tunneling transistor in silicon-on-insulator
- Complementary tunneling transistor for low power application
- Vertical tunnel field-effect transistor (IEEE Transactions on Electron Devices)
- Low-subthreshold-swing tunnel transistors (IEEE Electron Device Letters)
- Germanium-source tunnel field effect transistors with record high ION/IOFF (Symposium on VLSI Technology)
- The Tunnel Source (PNPN) n-MOSFET: A Novel High Performance Transistor (IEEE Transactions on Electron Devices)
- Steep Subthreshold Slope n- and p-Type Tunnel-FET Devices for Low-Power and Energy-Efficient Digital Circuits (IEEE Transactions on Electron Devices)
- FinFET-a self-aligned double-gate MOSFET scalable to 20 nm
- Double-Gate Strained-Ge Heterostructure Tunneling FET (TFET) With record high drive currents and ≪60mV/dec subthreshold slope (2008 IEEE International Electron Devices Meeting)
- Performance Enhancement of Vertical Tunnel Field-Effect Transistor with SiGe in the δp+ Layer
Their papers
- The Tunnel Source (PNPN) n-MOSFET: A Novel High Performance Transistor (2008) — 327 citations
- Lifetime of photogenerated carriers in silicon-on-insulator rib waveguides (2005) — 193 citations
- Effect of Pocket Doping and Annealing Schemes on the Source-Pocket Tunnel Field-Effect Transistor (2011) — 267 citations
- A 14nm logic technology featuring 2nd-generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 µm2 SRAM cell size (2014) — 604 citations