Effect of Pocket Doping and Annealing Schemes on the Source-Pocket Tunnel Field-Effect Transistor
By Ritesh Jhaveri, V. Nagavarapu, Jason C. S. Woo. IEEE Transactions on Electron Devices, 2011
267 citations recorded by the source corpus.
Subfields: Electrical and Electronic Engineering
View Paper: https://www.semanticscholar.org/paper/1a76dee78e59a3c54da6e2f6fae9fa0d329ea37d
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In Electrical and Electronic Engineering
- Mamidala Jagadesh Kumar
- D. Abdi
- Ru Huang
- Jason C. S. Woo
- Y. Qiu
- Qianqian Huang
- Runsheng Wang
- Shubham Sahay
Citations in the corpus
- Improved Subthreshold and Output Characteristics of Source-Pocket Si Tunnel FET by the Application of Laser Annealing (2013, background): “2(b), the TFETs with dopant pockets have smaller tunneling distances and sharp band banding due to enhanced lateral electric field in the tunneling junction resulting from the FD pocket between the source and the channel [1], [12].”
- In-Built N+ Pocket p-n-p-n Tunnel Field-Effect Transistor (2014, background): “Fulfilling the above requirements of realizing a narrow N+ pocket in a PNPN TFET is a technological challenge [9]–[11], [13].”
- A Comparative Study on the Impacts of Interface Traps on Tunneling FET and MOSFET (2014, methodology): “2312330 highly doped pocket geometry [9], and using the combined”