Controlling short-channel effects in deep-submicron SOI MOSFETs for improved reliability: a review

By Anurag Chaudhry, Mamidala Jagadesh Kumar. IEEE transactions on device and materials reliability, 2004

460 citations recorded by the source corpus.

This paper examines the performance degradation of a MOS device fabricated on silicon-on-insulator (SOI) due to the undesirable short-channel effects (SCE) as the channel length is scaled to meet the increasing demand for high-speed high-performing ULSI applications. The review assesses recent proposals to circumvent the SCE in SOI MOSFETs and a short evaluation of strengths and weaknesses specific to each attempt is presented. A new device structure called the dual-material gate (DMG) SOI MOSFET is discussed and its efficacy in suppressing SCEs such as drain-induced barrier lowering (DIBL), channel length modulation and hot-carrier effects, all of which affect the reliability of ultra-small geometry MOSFETs, is assessed.

Subfields: Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/5b953b642f15de02cc756fb51aada6c75b19146e

How researchers see this paper

The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.

In Electrical and Electronic Engineering

1. Mamidala Jagadesh Kumar
2. Anurag Chaudhry
3. M.Jagadesh Kumar1
4. G. Reddy
5. Sneh Saurabh

Citations in the corpus

• Investigation of the novel attributes of a fully depleted dual-material gate SOI MOSFET (2004, methodology): “A schematic cross-sectional view of an n-channel fully depleted DMG SOI MOSFET implemented in the 2-D device simulator MEDICI [ 10 ] is shown in Fig. 1 with gate metals M1 and M2 of lengths and , respectively.”
• A new dual-material double-gate (DMDG) nanoscale SOI MOSFET-two-dimensional analytical modeling and simulation (2005, background): “To enhance the immunity against short channel effects, a new structure called dual material gate (DMG) MOSFET was proposed [12-15].”