Length scaling of the Double Gate Tunnel FET with a high-K gate dielectric

By K. Boucart, Adrian M. Ionescu. 2007

333 citations recorded by the source corpus.

Subfields: Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/9de0c6247375b2626e0f6c8e6b5ba1f38908af5b

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In Electrical and Electronic Engineering

Citations in the corpus

Study of Random Dopant Fluctuation Effects in Germanium-Source Tunnel FETs (2011, neutral): “and drain, is scaled aggressively [12].”
Novel Attributes of a Dual Material Gate Nanoscale Tunnel Field-Effect Transistor (2011, background): “However, when L < 20 nm, the SMG-SDGTEFT does show significant VT rolloff [10], [17].”
Tunnel Field Effect Transistor With Raised Germanium Source (2010, background): “It should be noted that the fully elevated Ge-source TFETs can be scaled down to 10 nm in gate length without the OFF-state leakage degradation associated with conventional TFETs [11], due to the longer effective channel length provided by the Si vertical offset layer [see Fig.”
Junctionless Tunnel Field Effect Transistor (2013, methodology): “The high-k dielectric gate material for JL-TFETs is used to improve the ON current and SS.”
Pseudo-Two-Dimensional Model for Double-Gate Tunnel FETs Considering the Junctions Depletion Regions (2010, background): “It also leads to a higher slightly higher ON-current [13].”
In-Built N+ Pocket p-n-p-n Tunnel Field-Effect Transistor (2014, methodology): “We have calibrated our simulation models by reproducing the results reported in [22].”
Tunnel field-effect transistors as energy-efficient electronic switches (2011, background): “TFETs do not follow the same scaling rules as MOSFETs, in which many parameters must be scaled simultaneously to keep the same electric field throughout the devic”
Controlling Ambipolar Current in Tunneling FETs Using Overlapping Gate-on-Drain (2014, methodology): “We have calibrated our simulation models by reproducing the results reported in [4].”
On the Possibility of Obtaining MOSFET-Like Performance and Sub-60-mV/dec Swing in 1-D Broken-Gap Tunnel Transistors (2010, background): “ventional TFETs where the tunnel barrier dominates the overall device conductance [4], [5], [9], it can become a performance”
Steep Subthreshold Slope n- and p-Type Tunnel-FET Devices for Low-Power and Energy-Efficient Digital Circuits (2009, background): “Moreover, it has been shown that T-FETs can be scaled down to 20 nm in channel length, without much degradation of the subthreshold slope, ION and IOFF [7], [12], [14].”