Steep Subthreshold Slope n- and p-Type Tunnel-FET Devices for Low-Power and Energy-Efficient Digital Circuits

By Yasin Khatami, Kaustav Banerjee. IEEE Transactions on Electron Devices, 2009

340 citations recorded by the source corpus.

Subfields: Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/cf9b9d9d3fd979c874bf9645a45fcaebee3069e1

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In Electrical and Electronic Engineering

Citations in the corpus

Vertical Si-Nanowire $n$-Type Tunneling FETs With Low Subthreshold Swing ($\leq \hbox{50}\ \hbox{mV/decade}$ ) at Room Temperature (2011, background): “Enhancement in the ON current is possible by using lower bandgap material at the tunneling interface [1], [5]–[9], as well as high-k gate insulator [8], [10].”
CMOS-Compatible Vertical-Silicon-Nanowire Gate-All-Around p-Type Tunneling FETs With $\leq 50$-mV/decade Subthreshold Swing (2011, methodology): “Moreover, by using other known designs like heterostructure-based TFETs with smaller bandgap material at the tunneling interface [6] as well as high-k gate dielectrics [6], [8], one can achieve further enhancement in ON current.”
Study and Analysis of the Effects of SiGe Source and Pocket-Doped Channel on Sensing Performance of Dielectrically Modulated Tunnel FET-Based Biosensors (2016, background): “Presently, the tunnel FETs (TFETs) are regarded as one of the most promising alternatives of the conventional MOSFETs in several application areas [16]–[18].”
Comparative Performance Analysis of the Dielectrically Modulated Full- Gate and Short-Gate Tunnel FET-Based Biosensors (2015, background): “The tunnel FETs (TFETs) are emerging as the potential substitute for several gate engineered MOSFETs due to its superior performance in terms of speed, power dissipation, and subthreshold swing [17]–[20].”
Novel Attributes of a Dual Material Gate Nanoscale Tunnel Field-Effect Transistor (2011, background): “Tunnel Field Effect Transistors (TFETs) exhibit an excellent subthreshold swing and a very low leakage current and hence are being actively investigated for future low power CMOS applications [1-20].”
Impact of a Spacer Dielectric and a Gate Overlap/Underlap on the Device Performance of a Tunnel Field-Effect Transistor (2011, background): “Vertical n-channel and p-channel TFETs based on heterostructure silicon/intrinsicSiGe channel layers have been reported to have higher ON-state currents and lower subthreshold swings and threshold voltages [13].”
Effect of Pocket Doping and Annealing Schemes on the Source-Pocket Tunnel Field-Effect Transistor (2011, background): “15 V have been achieved in simulations [13].”
Low-Voltage Tunnel Transistors for Beyond CMOS Logic (2010, positive): “Designs have been proposed for both n [5], [46], [52], [ 53 ], [56] and p [53], [55] heterojunction TFETs, but costefficient integration approaches need more consideration.”