Two-dimensional analytical modeling of fully depleted DMG SOI MOSFET and evidence for diminished SCEs

By Mamidala Jagadesh Kumar, A. Chaudhry. IEEE Transactions on Electron Devices, 2004

272 citations recorded by the source corpus.

Subfields: Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/73a3b29494e6dcac8df703161f07e669d02b8523

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In Electrical and Electronic Engineering

1. Mansun Chan
2. Roy P. Paily
3. Ratul Kumar Baruah
4. Shengqi Yang

Citations in the corpus

• A Dual-Material Gate Junctionless Transistor With High- $k$ Spacer for Enhanced Analog Performance (2014, background): “The constants A1, A2, B1, and B2 are determined from boundary conditions 1) to 4) below [14], [23].”
• A Junctionless Nanowire Transistor With a Dual-Material Gate (2012, background): “increasing L1, leading to higher IV due to a stronger influence of drain voltage [9], [35].”