Kelin J. Kuhn
Electrical and Electronic Engineering · 2007–2012
A researcher in the Science corpus: 5 papers; trusts 8 researchers and is trusted by 4 researchers here, as inferred from the citation graph.
Subfields
- Electrical and Electronic Engineering — 51 citations into it; #3,549 of 16,539 by trust here, #6,474 by citations
- Biomedical Engineering — 13 citations into it
- Materials Chemistry — 6 citations into it
- Atomic and Molecular Physics, and Optics — 5 citations into it
Whom Kelin J. Kuhn trusts overall
Their strongest outbound trust, strongest first, inferred from their citations.
- Massimo V. Fischetti
- J. Larson
- Isabelle Ferain
- Seonghoon Jin
- Roza Kotlyar
- Peide D. Ye
- Adelmo Ortiz-Conde
- Yi Xuan
- Neophytos Neophytou
- J. D. del Alamo
Who trusts Kelin J. Kuhn overall
Papers from Kelin J. Kuhn's perspective
Ordered by how strongly the researchers Kelin J. Kuhn trusts endorse each paper. Same corpus, a different order for every researcher.
- Review on high-k dielectrics reliability issues (IEEE transactions on device and materials reliability)
- Delaying forever: Uniaxial strained silicon transistors in a 90nm CMOS technology (Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004.)
- Mechanical stress effect of etch-stop nitride and its impact on deep submicron transistor design (International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138))
- Effective electron mobility in Si inversion layers in metal–oxide–semiconductor systems with a high-κ insulator: The role of remote phonon scattering
- Mechanism of Electron Trapping and Characteristics of Traps in $\hbox{HfO}_{2}$ Gate Stacks (IEEE transactions on device and materials reliability)
- High-κ gate dielectrics: Current status and materials properties considerations
- A critical examination of the mechanics of dynamic NBTI for PMOSFETs (IEEE International Electron Devices Meeting 2003)
- A review of recent MOSFET threshold voltage extraction methods (Microelectronics and reliability)
- Pi-Gate SOI MOSFET (IEEE Electron Device Letters)
- Intrinsic parameter fluctuations in decananometer MOSFETs introduced by gate line edge roughness
Their papers
- Comparison of Junctionless and Conventional Trigate Transistors With $L_{g}$ Down to 26 nm (2011) — 329 citations
- A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging (2007) — 872 citations
- Process Technology Variation (2011) — 348 citations
- Considerations for Ultimate CMOS Scaling (2012) — 612 citations
- BTI reliability of 45 nm high-K + metal-gate process technology (2008) — 133 citations