Delaying forever: Uniaxial strained silicon transistors in a 90nm CMOS technology

By K. Mistry, M. Armstrong, P. AuthChristopher, S. Cea, T. Coan, Tahir Ghani, T. Hoffmann, A. Murthy, J. Sandford, R. Shaheed and 4 more. Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004., 2004

160 citations recorded by the source corpus.

Subfields: Biomedical Engineering, Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/ba14571bc3961bc92d7ae325723858203ad44886

How researchers see this paper

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In Biomedical Engineering

1. Kelin J. Kuhn

In Electrical and Electronic Engineering

1. Kelin J. Kuhn
2. Lucian Shifren
3. Igor L. Markov
4. Bevan M. Baas
5. Aaron Stillmaker
6. Qiang Li
7. Kei May Lau

Citations in the corpus

• Fundamentals of silicon material properties for successful exploitation of strain engineering in modern CMOS manufacturing (2006, methodology): “Therefore, this method is often called the uniaxial strain technique [8].”
• In search of "Forever," continued transistor scaling one new material at a time (2005, background): “Fig. 21. Ratio of external to channel resistance of a MOSFET estimated from [4]–[ 9 ].”
• A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging (2007, methodology): “PMOS performance is improved by using high-k+MG as well as by increasing the Ge content of the embedded SiGe to 30°O from 23% (65nm [8]) and 17% (9Onm [6]) and by reducing SiGe proximity to the channel.”
• A 30 Year Retrospective on Dennard's MOSFET Scaling Paper (2007, background): “In this case the new feature is selectively deposited SiGe source-drains to provide strained silicon for improved transistor performance [3].”