Considerations for Ultimate CMOS Scaling

By Kelin J. Kuhn. IEEE Transactions on Electron Devices, 2012

612 citations recorded by the source corpus.

Subfields: Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/76daa028c7f8f5184f76d0adee3a8856beeb06d7

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In Electrical and Electronic Engineering

1. Qiang Li
2. Bevan M. Baas
3. Aaron Stillmaker
4. Kei May Lau

Citations in the corpus

• Vertically stacked gate-all-around Si nanowire CMOS transistors with dual work function metal gates (2016, background): “INTRODUCTION Gate-all-around nanowire transistors enable ultimate CMOS device scaling [1].”
• Scaling equations for the accurate prediction of CMOS device performance from 180 nm to 7 nm (2017, methodology): “As transistors get smaller, however, shortchannel effects and other issues such as process variation start playing a larger role, making the traditional scaling equations inaccurate [4, 7, 10, 11].”
• Epitaxial growth of highly mismatched III-V materials on (001) silicon for electronics and optoelectronics (2017, positive): “Motivated by the development of III-V channel MOSFETs for high-performance and low-power logic applications, Huang et al. [54] and Orzali et al. [55] re- ported epitaxy of smooth In0.”