Review on high-k dielectrics reliability issues

By G. Ribes, J. Mitard, M. Denais, S. Bruyère, F. Monsieur, C. Parthasarathy, Emmanuel Vincent, Gerard Ghibaudo. IEEE transactions on device and materials reliability, 2005

519 citations recorded by the source corpus.

Subfields: Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/89f69f2b4293e5e65d83aeb1ba4b58132bbae685

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In Electrical and Electronic Engineering

Citations in the corpus

Mechanism of Electron Trapping and Characteristics of Traps in $\hbox{HfO}_{2}$ Gate Stacks (2007, background): “The kinetics of detrapping are similar to trapping [3], [4], [6], [8], while the actual Vt value after detrapping is defined by the detrapping voltage.”
Reliability Challenges for CMOS Technology Qualifications With Hafnium Oxide/Titanium Nitride Gate Stacks (2009, methodology): “In the case of NBTI, the power-law dependence has been explained by a hydrogen release process via multivibrational excitation [ 36 ].”
A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging (2007, background): “Many challenges with high-k integration have included VT pinning, mobility degradation due to soft optical phonons, and poor reliability [1-3].”
BTI reliability of 45 nm high-K + metal-gate process technology (2008, result): “This low Ea value is consistent with other reports on NMOS PBTI VT shift due to electron trapping in the HK bulk [10-11].”
Charge-Trapping Phenomena in HfO2-Based FeFET-Type Nonvolatile Memories (2016, background): “The mobility degradation [14], [15], VTH instability [8], [16] and reliability issues [17]–[19] (e.”