Intrinsic parameter fluctuations in decananometer MOSFETs introduced by gate line edge roughness

By Asen Asenov, Savas Kaya, Andrew R. Brown. 2003

624 citations recorded by the source corpus.

Subfields: Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/4d8d745632bc635b964590e5246adfd734730683

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In Electrical and Electronic Engineering

Citations in the corpus

FinFET Versus Gate-All-Around Nanowire FET: Performance, Scaling, and Variability (2018, methodology): “In order to achieve this, we have used Fourier synthesis with Gaussian autocorrelation [41] as described in [16] and [42].”
Poly-Si-Gate-Related Variability in Decananometer MOSFETs With Conventional Architecture (2007, background): “Such sources include random discrete dopants [7]–[9], line-edge roughness (LER) [10]–[12], interface roughness and oxide thickness variations [13], and the high-κ gate dielectric morphology [14], [15].”
Simulation Study of Individual and Combined Sources of Intrinsic Parameter Fluctuations in Conventional Nano-MOSFETs (2006, methodology): “Currently, with very few exceptions [ 13 ], [16], the impact of these sources has been studied using numerical simulations mainly in separation [14], [15], [17]–[23], and in idealized devices [4], [8], [13]–[17], [19], [21], or in more realistic devices corresponding to early or single technology ge”
High-performance CMOS variability in the 65-nm regime and beyond (2006, neutral): “The component of rVT due to LER should vary as 1/(Weff) , and simulations have generally shown this component to be small compared with the atomistic doping effect [3, 15].”
Statistical variability and reliability in nanoscale FinFETs (2011, methodology): “LER is obtained from Fourier synthesis with Gaussian autocorrelation, parameterised by correlation length (30nm) and root mean square (RMS) varied in the simulations [7].”
Simulation of intrinsic parameter fluctuations in decananometer and nanometer-scale MOSFETs (2003, methodology): “Simulations with both random discrete dopants and LER were carried out in [106] in order to understand the simul-”
Process Technology Variation (2011, background): “This group includes patterning proximity effects [both classical and optical proximity correction (OPC) [7]], line-edge roughness (LER) and linewidth roughness (LWR) [8], polish variations [shallow trench isolation (STI) [9] and gate [10]], and variations in the gate dielectric (oxide thickness vari”
Statistical Threshold-Voltage Variability in Scaled Decananometer Bulk HKMG MOSFETs: A Full-Scale 3-D Simulation Scaling Study (2011, methodology): “LER is introduced into the simulations using 1-D Fourier synthesis, which generates "random" lines using a Gaussian power spectrum [ 22 ].”