Mechanical stress effect of etch-stop nitride and its impact on deep submicron transistor design

By S. Ito, H. Namba, Kensuke Yamaguchi, Tsuyoshi Hirata, K. Ando, S. Koyama, Shunichiro Kuroki, N. Ikezawa, Tatsuya Suzuki, T. Saitoh and 1 more. International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138), 2000

160 citations recorded by the source corpus.

Subfields: Electrical and Electronic Engineering, Mechanics of Materials

View Paper: https://www.semanticscholar.org/paper/44dba16ed5acd5aba27831d36c5eb77e861073db

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In Electrical and Electronic Engineering

Citations in the corpus

Carrier-Transport-Enhanced Channel CMOS for Improved Power Consumption and Performance (2008, unknown): “[76]–[78] or compressive strain [79], [80], stress-memorization”
Uniaxial-process-induced strained-Si: extending the CMOS roadmap (2006, methodology): “First, high-stress capping layers deposited on MOSFETs were investigated as a technique to introduce stress into the channel [12], [13].”
A 90-nm logic technology featuring strained-silicon (2004, methodology): “Experimentally for uniaxial stressed Si, the mobility enhancement at high fields is observed for all work to date where the stress was introduced using a number of different techniques: mechanical wafer bending [43], nitride capping layer [25], [26], and the Si Ge adjacent to the channel [4]–[6] and”
Considerations for Ultimate CMOS Scaling (2012, background): “example, the SiN layers commonly used for contact etch stops can impart useful stress to the NMOS devices [150], [151] even in a replacement gate flow [152].”
A logic nanotechnology featuring strained-silicon (2004, background): “uniaxial strained-Si where the mobility enhancement is also observed at a high field: mechanical wafer bending [12] and nitride capping layer [5], [6].”