A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging

By K. Mistry, C. Allen, C. Auth, B. Beattie, D. Bergstrom, M. Bost, M. Brazier, M. Bühler, A. Cappellani, R. Chau and 44 more. 2007 IEEE International Electron Devices Meeting, 2007

872 citations recorded by the source corpus.

Subfields: Electrical and Electronic Engineering, Electronic, Optical and Magnetic Materials

View Paper: https://www.semanticscholar.org/paper/69b12b11611b2195920b103e627d3f576d335648

How researchers see this paper

The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.

In Electrical and Electronic Engineering

1. Nan Zhang
2. Shailendra Jain
3. S. Thompson
4. Kelin J. Kuhn
5. Kornel F. Ehmann
6. Fengzhou Fang
7. Bevan M. Baas
8. Aaron Stillmaker

In Electronic, Optical and Magnetic Materials

1. Nan Zhang

Citations in the corpus

• A 48-Core IA-32 message-passing processor with DVFS in 45nm CMOS (2010, positive): “The die area is 567mm(2) and is implemented in 45nm high-κ metal-gate CMOS [2].”
• Strain: A Solution for Higher Carrier Mobility in Nanoscale MOSFETs (2009, methodology): “With the successful integration and performance of strained devices in 90- and 65-nm nodes, third-generation strained Si technology was incorporated into the 45-nm logic technology (123).”
• Towards atomic and close-to-atomic scale manufacturing (2019, background): “It has been widely used in the energy conversion industry (photovoltaics, fuel cells) [109, 110] and the semiconductor industry (high-k transistors) [111, 112], as one of the process chains integrated into existing product production.”
• Considerations for Ultimate CMOS Scaling (2012, background): “or replacement gate technique [82]–[88].”