Tahir Ghani
Atomic and Molecular Physics, and Optics · 2000–2014
A researcher in the Science corpus: 12 papers; trusts 1 researcher and is trusted by 0 researchers here, as inferred from the citation graph.
Subfields
- Atomic and Molecular Physics, and Optics — 13 citations into it
Whom Tahir Ghani trusts
Their strongest outbound trust, strongest first, inferred from their citations.
- J. Miltat (in Atomic and Molecular Physics, and Optics)
Papers from Tahir Ghani's perspective
Ordered by how strongly the researchers Tahir Ghani trusts endorse each paper. Same corpus, a different order for every researcher.
- Six-band k⋅p calculation of the hole mobility in silicon inversion layers: Dependence on surface orientation, strain, and silicon thickness
- Mechanical stress effect of etch-stop nitride and its impact on deep submicron transistor design (International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138))
- Cramming More Components Onto Integrated Circuits
- A logic nanotechnology featuring strained-silicon (IEEE Electron Device Letters)
- Characteristics and device design of sub-100 nm strained Si N- and PMOSFETs (2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303))
- Strained Si NMOSFETs for high performance CMOS technology (2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184))
- A 90nm high volume manufacturing logic technology featuring novel 45nm gate length strained silicon CMOS transistors (IEEE International Electron Devices Meeting 2003)
- Strained silicon MOSFET technology (Digest. International Electron Devices Meeting,)
- Electronics
- Key differences for process-induced uniaxial vs. substrate-induced biaxial stressed Si and Ge channel MOSFETs (IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004.)
Their papers
- A 90-nm logic technology featuring strained-silicon (2004) — 671 citations
- The High-k Solution (2007) — 329 citations
- Scaling challenges and device design requirements for high performance sub-50 nm gate length planar CMOS transistors (2000) — 188 citations
- A logic nanotechnology featuring strained-silicon (2004) — 488 citations
- In search of "Forever," continued transistor scaling one new material at a time (2005) — 176 citations
- A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging (2007) — 872 citations
- A 90nm high volume manufacturing logic technology featuring novel 45nm gate length strained silicon CMOS transistors (2003) — 590 citations
- A 22nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density MIM capacitors (2012) — 686 citations
- Delaying forever: Uniaxial strained silicon transistors in a 90nm CMOS technology (2004) — 160 citations
- A 14nm logic technology featuring 2nd-generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 µm2 SRAM cell size (2014) — 604 citations
- Proposal of a Spin Torque Majority Gate Logic (2010) — 157 citations
- BTI reliability of 45 nm high-K + metal-gate process technology (2008) — 133 citations