Strained Si NMOSFETs for high performance CMOS technology

By K. Rim, S. J. Koester, Michael J. Hargrove, J. Chu, Patricia M. Mooney, John A. Ott, T. Kanarsky, P. Ronsheim, M. Ieong, A. Grill and 1 more. 2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184), 2001

147 citations recorded by the source corpus.

Subfields: Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/2e46749c1049ec7fe9ba056761f4614b73a95628

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In Electrical and Electronic Engineering

1. Lucian Shifren
2. Mark T. Bohr

Citations in the corpus

• Fundamentals of silicon material properties for successful exploitation of strain engineering in modern CMOS manufacturing (2006, unknown): “densities as measured experimentally [16], [138], [139].”
• Electrical characterization of germanium p-channel MOSFETs (2003, background): “Enhanced device performances have been demonstrated by using a strained Si channel grown upon a relaxed silicon germanium (SiGe) substrate, where the electron mobility is increased due to the reduced intervalley phonon scattering [ 1 ].”
• A 90-nm logic technology featuring strained-silicon (2004, methodology): “Lastly, since the Si Ge is located only in the source/drain versus the entire substrate, the MOSFET self-heating for this structure (unlike biaxial strain) [18] is unchanged.”