A 90-nm logic technology featuring strained-silicon

By S. Thompson, M. Armstrong, C. Auth, M. Alavi, M. Buehler, Robert Chau, S. Cea, Tahir Ghani, G. Glass, T. Hoffman and 18 more. IEEE Transactions on Electron Devices, 2004

671 citations recorded by the source corpus.

Subfields: Biomedical Engineering, Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/29372a0e6d77f4f69a58d16bba43415618a2c5ec

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Citations in the corpus

Junctionless Transistors: Physics and Properties (2011, background): “Since Eeff increases when the effective oxide thickness, EOT, is reduced, surface channel mobility has steadily decreased in successive technology nodes [10] and would now be well below 100 cm/Vs at the 45-nm node, if it wasn’t for the introduction of strained silicon technology: dealing with mobili”
Flexible, Foldable, Actively Multiplexed, High-Density Electrode Array for Mapping Brain Activity in vivo (2011, background): “1f ) and was maintained well below the mechanical fracture strain of each inorganic material (∼1% for Si and SiO 2”
Strain engineering of two‐dimensional materials: Methods, properties, and applications (2021, background): “For example, when the uniaxial or biaxial tensile strain is applied to the channel of a silicon transistor, the electron mobility (or hole mobility) can be greatly enhanced.(19) However, traditional semiconductor bulk single crystals only withstand very limited strain, which largely limit the furthe”
In search of "Forever," continued transistor scaling one new material at a time (2005, background): “Lastly, to date strain enhanced mobility used in commercial production has been modest at about 500 MPa, leaving plenty of room for future improvements and strain to be engineered and introduced at many process steps [44].”
Considerations for Ultimate CMOS Scaling (2012, background): “vertical field (in contrast to tensile biaxial strain where the gains are significantly reduced at a higher vertical field [98], [99], [102], [103]).”