A 90nm high volume manufacturing logic technology featuring novel 45nm gate length strained silicon CMOS transistors

By Tahir Ghani, M. Armstrong, C. Auth, M. Bost, P. Charvat, G. Glass, T. Hoffmann, K. Johnson, C. Kenyon, J. Klaus and 10 more. IEEE International Electron Devices Meeting 2003, 2003

590 citations recorded by the source corpus.

Subfields: Biomedical Engineering, Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/8f736ac662c06d48b6fd1ce4a3f5a630c3f63bb4

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In Biomedical Engineering

Mark T. Bohr

In Electrical and Electronic Engineering

Citations in the corpus

A 90-nm logic technology featuring strained-silicon (2004, methodology): “Presently, with the introduction of 90-nm CMOS logic technologies and 45-nm transistors in 2003 [4]–[6], Moore’s law is found to still be valid in the nanotechnology era.”
Fundamentals of silicon material properties for successful exploitation of strain engineering in modern CMOS manufacturing (2006, background): “in the channel by SiGe deposition on the active regions beside the channel [5], [6].”
Physics of Hole Transport in Strained Silicon MOSFET Inversion Layers (2006, methodology): “More recently, due to its capability to retain most of the hole mobility gain at high effective field, uniaxial compressive stress has emerged as the preferred mobility enhancement method for PMOS for 90 nm [ 4 ], [5] and below technology nodes.”
In search of "Forever," continued transistor scaling one new material at a time (2005, methodology): “For Si Ge on an Si substrate used in [5], [15], and [28], and from (6) and (7), 1.”
Innovative Materials, Devices, and CMOS Technologies for Low-Power Mobile Multimedia (2008, methodology): “The highest improvements at the PMOS side have been obtained with SiGe source–drain regions [ 31 ] and with SiGe tunnel layer under the gate [32].”