A 22nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density MIM capacitors
By C. Auth, C. Allen, A. Blattner, D. Bergstrom, M. Brazier, M. Bost, M. Bühler, V. Chikarmane, Tahir Ghani, T. Glassman and 37 more. Symposium on VLSI Technology, 2012
686 citations recorded by the source corpus.
Subfields: Electrical and Electronic Engineering
View Paper: https://www.semanticscholar.org/paper/342be505e65489d12662dbbbb216790abb0b3b98
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In Electrical and Electronic Engineering
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Citations in the corpus
- Intrinsic transistor reliability improvements from 22nm tri-gate technology (2013, methodology): “The tri-gate transistor architecture introduced in Intel's 22nm process technology represents a radical departure from traditional planar transistors [1].”
- Overview of Beyond-CMOS Devices and a Uniform Methodology for Their Benchmarking (2013, background): “27 shows the historical trend of the metal 1 contacted gate pitch scaling with the process generations [65].”
- FIVR — Fully integrated voltage regulators on 4th generation Intel® Core™ SoCs (2014, background): “Decoupling for the input rail is provided by a combination of ceramic package capacitors and on-die MIM capacitors [6].”
- ASAP7: A 7-nm finFET predictive process design kit (2016, methodology): “T) SRAM requirements [40,46,56 – 58], so we used SRAM to help drive those DTCO design rule aspects.”
- Considerations for Ultimate CMOS Scaling (2012, methodology): “have been implemented successfully into manufacturing on the 22-nm node [2].”