In search of "Forever," continued transistor scaling one new material at a time

By Sandra E. Thompson, Robert S. Chau, Tahir Ghani, K. Mistry, Sulabh Tyagi, Mark Bohr. IEEE transactions on semiconductor manufacturing, 2005

176 citations recorded by the source corpus.

Subfields: Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/476761f6b2bf7c3efadbbde57f43979cec0bcfbf

How researchers see this paper

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In Electrical and Electronic Engineering

1. Claes Thelander
2. Lars Samuelson
3. Lars-Erik Wernersson
4. Tomas Bryllert
5. Bevan M. Baas
6. Aaron Stillmaker
7. C. Rehnstedt
8. L. Fröberg

Citations in the corpus

• Vertical Enhancement-Mode InAs Nanowire Field-Effect Transistor With 50-nm Wrap Gate (2008, background): “the gate partially, or fully, wraps around the transistor channel [1].”
• Vertical high-mobility wrap-gated InAs nanowire transistor (2006, background): “This eliminates the need for a complicated etch step to form the channel, as is necessary in many other types of wrap-gate architectures, for example, in Si FinFETs [4], [5].”
• Scaling equations for the accurate prediction of CMOS device performance from 180 nm to 7 nm (2017, background): “As transistors get smaller, however, short-channel effects and other issues such as process variation start playing a larger role, making the traditional scaling equations inaccurate [4,7,10,11].”