A 14nm logic technology featuring 2nd-generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 µm2 SRAM cell size

By S. Natarajan, M. Agostinelli, S. Akbar, M. Bost, A. Bowonder, V. Chikarmane, S. Chouksey, A. Dasgupta, K. Fischer, Q. Fu and 42 more. 2014 IEEE International Electron Devices Meeting, 2014

604 citations recorded by the source corpus.

Subfields: Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/efe7535b1dab0f9e215414f864efda0796b607f2

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In Electrical and Electronic Engineering

1. Ian A. Young
2. Lucian Shifren
3. Dmitri E. Nikonov

Citations in the corpus

• ASAP7: A 7-nm finFET predictive process design kit (2016, methodology): “T) SRAM requirements [40,46,56 – 58], so we used SRAM to help drive those DTCO design rule aspects.”
• Benchmarking of Beyond-CMOS Exploratory Devices for Logic Integrated Circuits (2015, methodology): “SUCCESSFUL scaling of CMOS field-effect transistors (FETs) has occurred over more than four decades according to the cadence of Moore’s law [1] and has now reached gate lengths of 20 nm in [2].”