A logic nanotechnology featuring strained-silicon

By S. Thompson, M. Armstrong, C. Auth, S. Cea, R. Chau, G. Glass, T. Hoffman, J. Klaus, Z. Ma, B. Mcintyre and 9 more. IEEE Electron Device Letters, 2004

488 citations recorded by the source corpus.

Subfields: Biomedical Engineering, Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/3056a6975f06a12514997719ae5d078c77faf96f

How researchers see this paper

The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.

In Biomedical Engineering

1. R. Chau
2. Yang Yang
3. A. O'Neill
4. Claudio Fiegna
5. Mark T. Bohr
6. Enrico Sangiorgi

In Electrical and Electronic Engineering

1. R. Chau
2. Lucian Shifren
3. Yang Yang
4. A. O'Neill
5. Claudio Fiegna
6. S. Thompson
7. Jerry G. Fossum
8. Mark T. Bohr

Citations in the corpus

• Analysis of Self-Heating Effects in Ultrathin-Body SOI MOSFETs by Device Simulation (2008, background): “of the channel region can improve channel mobility [9], [10], thus increasing the ION/IOFF ratio.”
• In search of "Forever," continued transistor scaling one new material at a time (2005, methodology): “improvement over state-of-the-art 45- [28] or 35-nm [29] transistors currently in high volume production.”
• Benchmarking nanotechnology for high-performance and low-power logic transistor applications (2004, background): “8 shows the subthreshold slope of planar Si FETs, nonplanar Si FETs (e.g., Tri-gate transistors [5], [6]), CNT FETs, and planar III–”
• Uniaxial-process-induced strained-Si: extending the CMOS roadmap (2006, methodology): “The hole piezoresistance coefficient is largest for longitudinal compression along 〈110〉 for both (001) and (110) wafers consistent with the industry primarily using 〈110〉 channel direction in strained-Si technologies [4], [22], [29].”
• Carrier-Transport-Enhanced Channel CMOS for Improved Power Consumption and Performance (2008, unknown): “SiGe-embedded source/drain [33]–[35], [73], SiC-embedded source/drain [74], [75], contact-etch stop liners with tensile”
• Fundamentals of silicon material properties for successful exploitation of strain engineering in modern CMOS manufacturing (2006, background): “mobility [9] and build production worthy PMOS transistors.”
• Comparison of threshold-voltage shifts for uniaxial and biaxial tensile-stressed n-MOSFETs (2004, background): “Alternatively, electron mobility enhancement can be obtained using longitudinal uniaxial tensile stress typically introduced with a nitride capping layer [5], [10], [11].”
• A 90-nm logic technology featuring strained-silicon (2004, methodology): “Presently, with the introduction of 90-nm CMOS logic technologies and 45-nm transistors in 2003 [4]–[6], Moore’s law is found to still be valid in the nanotechnology era.”
• The end of CMOS scaling: toward the introduction of new materials and structural changes to improve MOSFET performance (2005, background): “Transport-enhanced MOSFETs [2]–[16] are those structures for which increased transistor drive current for improved circuit performance can be achieved by enhancing the average velocity of carriers in the channel.”