Scaling challenges and device design requirements for high performance sub-50 nm gate length planar CMOS transistors
By Tahir Ghani, K. Mistry, P. Packan, S. Thompson, M. Stettler, S. Tyagi, Mark T. Bohr. 2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104), 2000
188 citations recorded by the source corpus.
Subfields: Electrical and Electronic Engineering
View Paper: https://www.semanticscholar.org/paper/153a68a8e757fff19a078067ea7220c9ff477b36
How researchers see this paper
The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.
In Electrical and Electronic Engineering
- Evans M. Harrell II
- James D. Meindl
- Qiang Chen
- Edward J. Nowak
- Yuan Taur
- Ethan C. Ahn
- Kaushik Roy
- A. Naeemi
Citations in the corpus
- Device scaling limits of Si MOSFETs and their application dependencies (2001, background): “15, the tunneling current density is on the order of 1 A/cm(Fig.”
- A physical short-channel threshold voltage model for undoped symmetric double-gate MOSFETs (2003, background): “In DG MOSFETs, however, the ultrathin silicon channel is preferred to be undoped (i.e., lightly doped with cm [7]) to avoid adverse effects associated with heavy doping, such as mobility degradation [ 8 ] and random microscopic fluctuations of dopant atoms [9].”