Characteristics and device design of sub-100 nm strained Si N- and PMOSFETs

By Kern Rim, J. O. Chu, Huajie Chen, Keith A. Jenkins, T. Kanarsky, K. Lee, Anda C. Mocuta, Huilong Zhu, R. Roy, J. Newbury and 9 more. 2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303), 2002

152 citations recorded by the source corpus.

Subfields: Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/e7bcd76e190f880c14933453d926b01cec0c7240

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In Electrical and Electronic Engineering

1. Lucian Shifren
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Citations in the corpus

• Three-dimensional integrated circuits (2006, unknown): “enhancement have been demonstrated [7], but future”
• Hybrid-orientation technology (HOT): opportunities and challenges (2006, background): “modifications such as STI, source/drain, and contact etch-stop film has been widely investigated on (100) planes [10]–[15].”
• Electrical characterization of germanium p-channel MOSFETs (2003, background): “However, at low Ge content, only moderate increases in hole mobility could be achieved in strained Si compared to bulk Si [ 2 ].”
• Performance dependence of CMOS on silicon substrate orientation for ultrathin oxynitride and HfO2 gate dielectrics (2003, background): “Unlike strained-silicon CMOS with mostly electron mobility enhancement [14], resulting in pMOS performance lagging further behind nMOS, the drive current of nMOS and pMOS on (110)”
• A 90-nm logic technology featuring strained-silicon (2004, background): “For low to moderate biaxial stress, the piezoresistance coefficient predicts a slight mobility degradation which is consistent with the biaxial stress experimental data [19], [20] (see Fig.”