A comprehensive framework for predictive modeling of negative bias temperature instability

By Srinivasan Chakravarthi, Anand T. Krishnan, Vijay Reddy, C. Machala, Sridhar Krishnan. 2004 IEEE International Reliability Physics Symposium. Proceedings, 2004

333 citations recorded by the source corpus.

Subfields: Atomic and Molecular Physics, and Optics, Electrical and Electronic Engineering, Mechanics of Materials

View Paper: https://www.semanticscholar.org/paper/e7c5e27ba783f41489591808025ddc80c2c1aedb

How researchers see this paper

The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.

In Atomic and Molecular Physics, and Optics

In Electrical and Electronic Engineering

In Mechanics of Materials

Citations in the corpus

On the generation and recovery of interface traps in MOSFETs subjected to NBTI, FN, and HCI stress (2006, methodology): “R–D model can explain the (relatively) lower n of NIT generation during NBTI stress as due to release and diffusion of either or both neutral H and H2 species [18].”
Analysis of NBTI Degradation- and Recovery-Behavior Based on Ultra Fast VT-Measurements (2006, background): “A discussion of thin oxide effects and numerical results are given in [5] and [6].”
A comprehensive model for PMOS NBTI degradation: Recent progress (2007, background): “(Bottom) Measurement with variable delay [8,17,18] support the theoretical interpretation.”
Compact Modeling and Simulation of Circuit Reliability for 65-nm CMOS Technology (2007, background): “To date, research work on NBTI and CHC has been active only within the communities of device and reliability physics [2]–[4], [8], [17].”
Stochastic charge trapping in oxides: From random telegraph noise to bias temperature instabilities (2012, background): “The model has seen a number of refinements during the last couple of years [18,80,81], with the current version relying on the diffusion of neutral H2.”
The negative bias temperature instability in MOS devices: A review (2006, methodology): “This form is used by some groups [63], while an empirical power-law form form such as E ox [14,64] or E4ox [41] (Fig.”
Recent Issues in Negative-Bias Temperature Instability: Initial Degradation, Field Dependence of Interface Trap Generation, Hole Trapping Effects, and Relaxation (2007, background): “I. INTRODUCTION N EGATIVE-BIAS temperature instability (NBTI), as thename suggests, indicates a temperature-accelerated degradation in PMOS devices when it is stressed with negative gate voltage.”
A Comparative Study of Different Physics-Based NBTI Models (2013, methodology): “The H/H2 RD model for ΔNIT [8], [18], [19], [41] and the framework of uncorrelated ΔNIT, ΔNHT, and ΔNOT [11], [14] are discussed in Section IV to explain dc stress and recovery.”
Modeling and minimization of PMOS NBTI effect for robust nanometer design (2006, background): “Indeed, as gate oxide gets thinner than 4nm, the threshold voltage change caused by NBTI for the PMOS transistor has become the dominant factor to limit the life time, which is much shorter than that defined by hot-carrier induced degradation (HCI) of the NMOS transistor [2].”
On the Physical Mechanism of NBTI in Silicon Oxynitride p-MOSFETs: Can Differences in Insulator Processing Conditions Resolve the Interface Trap Generation versus Hole Trapping Controversy? (2007, methodology): “15 shows time evolution of overall ∆VT and contribution by ∆Nh and ∆NIT for thick TNO device, obtained by numerically solving (3) and the R-D model [16],[25],[27], respectively.”
Compact Modeling of MOSFET Wearout Mechanisms for Circuit-Reliability Simulation (2008, methodology): “Taking into account all of the earlier relations, ∆Vt(t) is often modeled as [77], [ 78 ]”
Investigation and modeling of interface and bulk trap generation during negative bias temperature instability of p-MOSFETs (2004, methodology): “Finally, it has been recently shown [31] that the solution of the R-D equation with neutral and results in a time power law between 0.”