Investigation and modeling of interface and bulk trap generation during negative bias temperature instability of p-MOSFETs

By Souvik Mahapatra, P. B. Kumar, M. A. Alam. IEEE Transactions on Electron Devices, 2004

220 citations recorded by the source corpus.

Subfields: Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/59d4c49e204142dad100c2bb8f57b300f5797d3a

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In Electrical and Electronic Engineering

Citations in the corpus

The Impact of NBTI Effect on Combinational Circuit: Modeling, Simulation, and Analysis (2010, background): “where is the time exponent parameter, and for diffusion, it is 1/6; has a temperature dependence as [4], is the activation energy of hydrogen species, is the Boltzmann constant, is constant parameter with the value of s nm , is a constant parameter, is the vertical electrical field, and is a technol”
On the generation and recovery of interface traps in MOSFETs subjected to NBTI, FN, and HCI stress (2006, background): “the latter stress conditions [4], [7], [10].”
Compact Modeling and Simulation of Circuit Reliability for 65-nm CMOS Technology (2007, background): “C has a temperature dependence as C = T−1 o exp(−Ea/kT ) [20], k being the Boltzmann’s constant and To being another constant.”
A comprehensive model for PMOS NBTI degradation: Recent progress (2007, background): “However, generalized scaling arguments consistently showed that EA ED/n [1,4], with EF ER [1,2,4,28].”
A Comparative Study of Different Physics-Based NBTI Models (2013, methodology): “5) Several techniques have been used for direct estimation of trap generation during NBTI—at Si/SiO2 and SiO2/polySi interfaces using low-voltage (LV) stress-induced leakage current (SILC) [19], [36], at and near the Si/SiO2 interface by DCIV [14], [36]–[38] and charge pumping (CP) [4], [5], [7], an”
Impact of NBTI on SRAM read stability and design for reliability (2006, methodology): “can be solved for the steady state condition dNIT dt = 0 to obtain an expression for NIT as derived in [3] and [17]: NIT =rkfN0 kr (Dt)0:25: (3)”
On the Physical Mechanism of NBTI in Silicon Oxynitride p-MOSFETs: Can Differences in Insulator Processing Conditions Resolve the Interface Trap Generation versus Hole Trapping Controversy? (2007, methodology): “12 shows the T activation of lifetime (at fixed ∆VT) from on-the-fly IDLIN (thin and thick PNO, thin PNO) and CP (thick PNO and thick TNO) measurements, obtained by lateral scaling of ∆VT versus t data (plotted in a log-log scale) [6],[15].”