Dhanoop Varghese
Electrical and Electronic Engineering · 2007
A researcher in the Science corpus: 2 papers; trusts 2 researchers and is trusted by 1 researcher here, as inferred from the citation graph.
Subfields
- Electrical and Electronic Engineering — 32 citations into it; #15,955 of 16,539 by trust here, #12,348 by citations
Whom Dhanoop Varghese trusts overall
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Who trusts Dhanoop Varghese overall
Papers from Dhanoop Varghese's perspective
Ordered by how strongly the researchers Dhanoop Varghese trusts endorse each paper. Same corpus, a different order for every researcher.
- Disorder-controlled-kinetics model for negative bias temperature instability and its experimental verification (2005 IEEE International Reliability Physics Symposium, 2005. Proceedings. 43rd Annual.)
- Characterization and Physical Origin of Fast Vth Transient in NBTI of pMOSFETs with SiON Dielectric (International Electron Devices Meeting)
- Material dependence of hydrogen diffusion: implications for NBTI degradation (IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.)
- On the Physical Mechanism of NBTI in Silicon Oxynitride p-MOSFETs: Can Differences in Insulator Processing Conditions Resolve the Interface Trap Generation versus Hole Trapping Controversy? (2007 IEEE International Reliability Physics Symposium Proceedings. 45th Annual)
- Universal recovery behavior of negative bias temperature instability [PMOSFETs] (IEEE International Electron Devices Meeting 2003)
- A comprehensive framework for predictive modeling of negative bias temperature instability (2004 IEEE International Reliability Physics Symposium. Proceedings)
- Analysis of NBTI Degradation- and Recovery-Behavior Based on Ultra Fast VT-Measurements (2006 IEEE International Reliability Physics Symposium Proceedings)
- A comprehensive model for PMOS NBTI degradation: Recent progress (Microelectronics and reliability)
- A comprehensive model of PMOS NBTI degradation (Microelectronics and reliability)
- Negative bias temperature instability: Road to cross in deep submicron silicon semiconductor manufacturing