A comprehensive model for PMOS NBTI degradation: Recent progress
By M. A. Alam, Haldun Kufluoglu, Dhanoop Varghese, Souvik Mahapatra. Microelectronics and reliability, 2007
297 citations recorded by the source corpus.
Subfields: Electrical and Electronic Engineering
View Paper: https://www.semanticscholar.org/paper/7624e4f940d4e9d46b214c818f8cff47131de0a9
How researchers see this paper
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In Electrical and Electronic Engineering
- Tibor Grasser
- Souvik Mahapatra
- M. A. Alam
- Haldun Kufluoglu
- Dhanoop Varghese
- A. E. Islam
- Ben Kaczer
- Jin Qin
Citations in the corpus
- Recent Issues in Negative-Bias Temperature Instability: Initial Degradation, Field Dependence of Interface Trap Generation, Hole Trapping Effects, and Relaxation (2007, background): “I. INTRODUCTION N EGATIVE-BIAS temperature instability (NBTI), as thename suggests, indicates a temperature-accelerated degradation in PMOS devices when it is stressed with negative gate voltage.”
- The Universality of NBTI Relaxation and its Implications for Modeling and Characterization (2007, background): “In particular, the value of the extracted power-law exponent depends significantly on the delay introduced during the measurement [5] [17] [21].”
- Compact Modeling of MOSFET Wearout Mechanisms for Circuit-Reliability Simulation (2008, result): “The same equation can be easily derived from the reformatted reaction‐diffusion model by assuming that the interfacetrap saturation is caused by depletion of all Si−H bonds [ 64 ].”