A comprehensive model of PMOS NBTI degradation

By M. A. Alam, Souvik Mahapatra. Microelectronics and reliability, 2005

781 citations recorded by the source corpus.

Subfields: Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/79b4723a010c66c2f3fdcd3bd79dba1c3a3e2d28

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In Electrical and Electronic Engineering

Citations in the corpus

Review and Reexamination of Reliability Effects Related to NBTI-Induced Statistical Variations (2007, background): “2) It is now recognized that there are concurrent interface state repassivation (a prominent feature of the Reaction-Diffusion Model [26]), and oxide trap detrapping processes occurring (as shown by fast recovery effects [27]).”
Predictive Modeling of the NBTI Effect for Reliable Design (2006, background): “Firstly, oxide thickness was assumed to be infinite and the polysilicon was considered either as a reflector or absorber [1].”
Radiative sky cooling: fundamental physics, materials, structures, and applications (2017, neutral): “Note that most of the degradation mechanisms in electronics such as negativebias temperature instability [107] or electromigration [108] depend on temperature exponentially.”
Compact Modeling of MOSFET Wearout Mechanisms for Circuit-Reliability Simulation (2008, background): “The up-to-date concept and a reaction‐diffusionprocess (R−D model [ 63 ])-based physical model [65], [66] are discussed in this paper.”
The Impact of NBTI Effect on Combinational Circuit: Modeling, Simulation, and Analysis (2010, background): “In the reaction phase, some Si–H bonds at the Si–SiO interface are broken under the vertical electrical stress [9], [14], [15].”
Impact of NBTI on the temporal performance degradation of digital circuits (2005, background): “Thus, depends on the hole density , hole capture cross-section , tunneling coefficient , and the bond dissociation coefficient , and can be expressed as , where and depend on the electric field across the oxide, is the field acceleration factor, , , and are assumed to have weak field dependence [10]”
Recent Issues in Negative-Bias Temperature Instability: Initial Degradation, Field Dependence of Interface Trap Generation, Hole Trapping Effects, and Relaxation (2007, background): “I. INTRODUCTION N EGATIVE-BIAS temperature instability (NBTI), as thename suggests, indicates a temperature-accelerated degradation in PMOS devices when it is stressed with negative gate voltage.”
A comprehensive model for PMOS NBTI degradation: Recent progress (2007, methodology): “The conclusion of dispersive transport has been based on classical measurement technique with measurement delays of 200 ms [2,20] 500 ms [1].”
Mechanism of Electron Trapping and Characteristics of Traps in $\hbox{HfO}_{2}$ Gate Stacks (2007, methodology): “To avoid a distortion of the ∆Vt(t) dependence caused by the ∆Vt relaxation during stress interruptions, the stress periods between the Id–Vg measurements were kept constant: under this condition, charge detrapping may affect an absolute value of the measured Vt rather than the shape of the ∆Vt(t) c”
Compact Modeling and Simulation of Circuit Reliability for 65-nm CMOS Technology (2007, background): “It is also proportional to the density of reaction species, namely holes or hot electrons [4], [7], [29].”
The negative bias temperature instability in MOS devices: A review (2006, methodology): “Numerical simulations have given values that are both somewhat larger [61] and smaller [63].”
Security of IoT systems: Design challenges and opportunities (2014, methodology): “Speciﬁcally, device aging through techniques such as NBTI can permanently alter the fabrication, but can be made identical through a novel matching procedure This procedure is executed in such a way that only the two participating PPUFs become identical while it is probabilistically negligible that…”
On the Physical Mechanism of NBTI in Silicon Oxynitride p-MOSFETs: Can Differences in Insulator Processing Conditions Resolve the Interface Trap Generation versus Hole Trapping Controversy? (2007, methodology): “12 shows the T activation of lifetime (at fixed ∆VT) from on-the-fly IDLIN (thin and thick PNO, thin PNO) and CP (thick PNO and thick TNO) measurements, obtained by lateral scaling of ∆VT versus t data (plotted in a log-log scale) [6],[15].”
Negative bias temperature instability: What do we understand? (2007, background): “, the gate voltages on n- and p-channel devices are not the same for a given oxide electric field [5].”
Modeling and minimization of PMOS NBTI effect for robust nanometer design (2006, background): “Indeed, as gate oxide gets thinner than 4nm, the threshold voltage change caused by NBTI for the PMOS transistor has become the dominant factor to limit the life time, which is much shorter than that defined by hot-carrier induced degradation (HCI) of the NMOS transistor [2].”