Scaling the vertical tunnel FET with tunnel bandgap modulation and gate workfunction engineering

By K. K. Bhuwalka, Jörg Schulze, Ignaz Eisele. IEEE Transactions on Electron Devices, 2005

359 citations recorded by the source corpus.

Subfields: Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/9dcffe8036504829fc0d0e03e7c971e011637b23

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In Electrical and Electronic Engineering

Citations in the corpus

On the Possibility of Obtaining MOSFET-Like Performance and Sub-60-mV/dec Swing in 1-D Broken-Gap Tunnel Transistors (2010, background): “ventional TFETs where the tunnel barrier dominates the overall device conductance [4], [5], [9], it can become a performance”
The Tunnel Source (PNPN) n-MOSFET: A Novel High Performance Transistor (2008, background): “structures [14], is greatly reduced in the PNPN n-MOSFET.”
Novel Attributes of a Dual Material Gate Nanoscale Tunnel Field-Effect Transistor (2011, background): “the source and drain doping profiles as abrupt throughout our simulations as in earlier works [4], [5], [10], [12], [15].”
Study and Analysis of the Effects of SiGe Source and Pocket-Doped Channel on Sensing Performance of Dielectrically Modulated Tunnel FET-Based Biosensors (2016, background): “can be improved by either structural or material engineering schemes [16], [17], [27]–[34].”
Length scaling of the Double Gate Tunnel FET with a high-K gate dielectric (2007, methodology): “have already explained this [9–11] as the effect of Zener breakdown, meaning that electron tunneling still takes place when it should not, in the OFF-state.”
Double-Gate Tunnel FET With High-$\kappa$ Gate Dielectric (2007, positive): “One such reported device is the Tunnel FET that incorporates a delta-layer of SiGe at the edge of the p+ region, in order to reduce the barrier width and, thereby, improve the subthreshold swing and ON-current [10], [11].”
Design of Tunneling Field-Effect Transistors Using Strained-Silicon/Strained-Germanium Type-II Staggered Heterojunctions (2008, methodology): “Although tunneling efficiency in silicon is poor due to the relatively large band gap (1.1 eV), simulations have been used to model TFETs with uniform reduced band gaps, such as SiGe with Eg ∼ 0.9 eV [6], [ 7 ].”
A Compact 2-D Analytical Model for Electrical Characteristics of Double-Gate Tunnel Field-Effect Transistors With a SiO2/High- $k$ Stacked Gate-Oxide Structure (2016, methodology): “A number of simulation based studies have been reported to improve the ION current by the structural modifications of the TFETs [9]–[11].”
Vertical Si-Nanowire $n$-Type Tunneling FETs With Low Subthreshold Swing ($\leq \hbox{50}\ \hbox{mV/decade}$ ) at Room Temperature (2011, background): “Enhancement in the ON current is possible by using lower bandgap material at the tunneling interface [1], [5]–[9], as well as high-k gate insulator [8], [10].”
Performance Comparison Between p-i-n Tunneling Transistors and Conventional MOSFETs (2008, background): “and/or heterojunction device geometries that have a small bandgap material only near the source tunneling region while a larger bandgap material is used in channel and drain regions in order to suppress OFF-state leakage [13], [16], [19].”
Impact of a Spacer Dielectric and a Gate Overlap/Underlap on the Device Performance of a Tunnel Field-Effect Transistor (2011, background): “[6], [10] reported that a TFET with a delta layer of SiGe at the edge of the source improves both ION and S.”
Steep Subthreshold Slope n- and p-Type Tunnel-FET Devices for Low-Power and Energy-Efficient Digital Circuits (2009, methodology): “layer of SiGe material can be used between the source and the channel [12].”
A Tunnel FET for $V_{DD}$ Scaling Below 0.6 V With a CMOS-Comparable Performance (2011, background): “ION can be increased by using lower band-gap materials at the source [9], using abrupt doping profiles at the source–channel interface”