Satyabrata Jit
Electrical and Electronic Engineering · 2016–2017
A researcher in the Science corpus: 2 papers; trusts 2 researchers and is trusted by 0 researchers here, as inferred from the citation graph.
Subfields
- Electrical and Electronic Engineering — 20 citations into it
Whom Satyabrata Jit trusts
Their strongest outbound trust, strongest first, inferred from their citations.
- Adrian M. Ionescu (in Electrical and Electronic Engineering)
- K. Boucart (in Electrical and Electronic Engineering)
Papers from Satyabrata Jit's perspective
Ordered by how strongly the researchers Satyabrata Jit trusts endorse each paper. Same corpus, a different order for every researcher.
- Double-Gate Tunnel FET With High-$\kappa$ Gate Dielectric (IEEE Transactions on Electron Devices)
- Tunnel field-effect transistor without gate-drain overlap
- A new definition of threshold voltage in Tunnel FETs
- Double-Gate Strained-Ge Heterostructure Tunneling FET (TFET) With record high drive currents and ≪60mV/dec subthreshold slope (2008 IEEE International Electron Devices Meeting)
- Tunneling Field-Effect Transistors (TFETs) With Subthreshold Swing (SS) Less Than 60 mV/dec (IEEE Electron Device Letters)
- Scaling the vertical tunnel FET with tunnel bandgap modulation and gate workfunction engineering (IEEE Transactions on Electron Devices)
- Complementary tunneling transistor for low power application
- Tunnel field-effect transistors as energy-efficient electronic switches (Nature)
- Tunnel Field Effect Transistor With Raised Germanium Source (IEEE Electron Device Letters)
- Modeling the single-gate, double-gate, and gate-all-around tunnel field-effect transistor
Their papers
- A Compact 2-D Analytical Model for Electrical Characteristics of Double-Gate Tunnel Field-Effect Transistors With a SiO2/High- $k$ Stacked Gate-Oxide Structure (2016) — 141 citations
- 2-D Analytical Modeling of the Electrical Characteristics of Dual-Material Double-Gate TFETs With a SiO2/HfO2 Stacked Gate-Oxide Structure (2017) — 160 citations