A Tunnel FET for $V_{DD}$ Scaling Below 0.6 V With a CMOS-Comparable Performance
By R. Asra, M. Shrivastava, Kota Murali, R. Pandey, H. Gossner, V. Rao. IEEE Transactions on Electron Devices, 2011
150 citations recorded by the source corpus.
Subfields: Electrical and Electronic Engineering
View Paper: https://www.semanticscholar.org/paper/db760a7b8f22470b30a049ef551604e04106b0fe
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In Electrical and Electronic Engineering
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Citations in the corpus
- Tunnel field-effect transistors as energy-efficient electronic switches (2011, background): “By overlapping the gate with the tunnelling region, or designing a source region covered with an epitaxial intrinsic channel layer under the top gate, I ON can be improved by a factor of more than 10 and a low S avg can be obtaine”
- Study and Analysis of the Effects of SiGe Source and Pocket-Doped Channel on Sensing Performance of Dielectrically Modulated Tunnel FET-Based Biosensors (2016, background): “can be improved by either structural or material engineering schemes [16], [17], [27]–[34].”