Design of Tunneling Field-Effect Transistors Using Strained-Silicon/Strained-Germanium Type-II Staggered Heterojunctions

By O. Nayfeh, C. N. Chléirigh, John Hennessy, L. Gomez, J. Hoyt, D. Antoniadis. IEEE Electron Device Letters, 2008

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Low-Voltage Tunnel Transistors for Beyond CMOS Logic (2010, unknown): “Heterojunction systems like SiGe/Si [46], AlGaSb/InAs [52], [55], and AlGaAsSb/InGaAs [56] boost the on-current.”
Performance Comparison Between p-i-n Tunneling Transistors and Conventional MOSFETs (2008, background): “silicon [13]–[19], as well as in carbon-nanotube (CNT)-based transistors [20]–[24].”
Direct and Indirect Band-to-Band Tunneling in Germanium-Based TFETs (2012, background): “So far, most research on Ge-based TFETs has merely considered the indirect transitions [6]–[17], and the default parameter file of the TCAD simulation”
Modeling of High-Performance p-Type III–V Heterojunction Tunnel FETs (2010, methodology): “Heterostructures with type-II interface represent the steepest possible p-n junctions and have therefore been investigated as TFET performance boosters in the Si/SiGe heterosystem [5], [8]–[10].”
Hetero-Gate-Dielectric Tunneling Field-Effect Transistors (2010, background): “On the other hand, it has been reported that TFETs have low ON-current Ion, which limits operation speed, and severe ambipolar behavior, which increases leakage current Iamb [4], [5].”
Improved Subthreshold and Output Characteristics of Source-Pocket Si Tunnel FET by the Application of Laser Annealing (2013, background): “in the linear region ID−VD characteristics [11], [15] caused by the large tunnel resistance across the tunneling junction.”