Zhixian Chen
Electrical and Electronic Engineering · 2011
A researcher in the Science corpus: 2 papers; trusts 4 researchers and is trusted by 0 researchers here, as inferred from the citation graph.
Subfields
- Electrical and Electronic Engineering — 18 citations into it
Whom Zhixian Chen trusts overall
Their strongest outbound trust, strongest first, inferred from their citations.
Papers from Zhixian Chen's perspective
Ordered by how strongly the researchers Zhixian Chen trusts endorse each paper. Same corpus, a different order for every researcher.
- Double-Gate Tunnel FET With High-$\kappa$ Gate Dielectric (IEEE Transactions on Electron Devices)
- Scaling the vertical tunnel FET with tunnel bandgap modulation and gate workfunction engineering (IEEE Transactions on Electron Devices)
- Vertical Silicon-Nanowire Formation and Gate-All-Around MOSFET (IEEE Electron Device Letters)
- Demonstration of Tunneling FETs Based on Highly Scalable Vertical Silicon Nanowires (IEEE Electron Device Letters)
- Impact of SOI, Si1-xGexOI and GeOI substrates on CMOS compatible Tunnel FET performance (2008 IEEE International Electron Devices Meeting)
- Si tunnel transistors with a novel silicided source and 46mV/dec swing (Symposium on VLSI Technology)
- Steep Subthreshold Slope n- and p-Type Tunnel-FET Devices for Low-Power and Energy-Efficient Digital Circuits (IEEE Transactions on Electron Devices)
- Band-to-band tunneling in carbon nanotube field-effect transistors. (Physical Review Letters)
- International Technology Roadmap for Semiconductors 2003の要求清浄度について － シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について －
- Performance Enhancement of Vertical Tunnel Field-Effect Transistor with SiGe in the δp+ Layer
Their papers
- CMOS-Compatible Vertical-Silicon-Nanowire Gate-All-Around p-Type Tunneling FETs With $\leq 50$-mV/decade Subthreshold Swing (2011) — 185 citations
- Vertical Si-Nanowire $n$-Type Tunneling FETs With Low Subthreshold Swing ($\leq \hbox{50}\ \hbox{mV/decade}$ ) at Room Temperature (2011) — 190 citations