Impact of a Spacer Dielectric and a Gate Overlap/Underlap on the Device Performance of a Tunnel Field-Effect Transistor

By Avik Chattopadhyay, Abhijit Mallik. IEEE Transactions on Electron Devices, 2011

155 citations recorded by the source corpus.

Subfields: Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/40f934d30d79aee786479aa408e0d51eb2b79e59

How researchers see this paper

The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.

In Electrical and Electronic Engineering

1. J. Madan
2. Rishu Chaujar

Citations in the corpus

• Interfacial Charge Analysis of Heterogeneous Gate Dielectric-Gate All Around-Tunnel FET for Improved Device Reliability (2016, methodology): “Abundant techniques have been explored for resolving this issue such as using a smaller band gap material in the source region such as germanium [1], hetero gate dielectric TFET [2], double gate architecture [3], gate to source overlap [4], gate to drain underlap [5], dual material gate [6], n-pocke”