FinFET-a self-aligned double-gate MOSFET scalable to 20 nm

By D. Hisamoto, Wen-Chin Lee, J. Kedzierski, H. Takeuchi, K. Asano, C. Kuo, E. Anderson, Tsu-Jae King, Jeffrey Bokor, Chenming Calvin Hu. 2000

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Nanoscale CMOS spacer FinFET for the terabit era (2002, background): “structures is the double-gate FinFET [1], [2] using a thin-body (Si-fin).”
Polymer self assembly in semiconductor microelectronics (2006, background): “designs are the finFET [140], the tri-gate FET [141], and”
Pi-Gate SOI MOSFET (2001, background): “1 shows the existing gate configuration for thin-film SOI MOSFETs: 1) single gate; 2) double gate; 3) triple gate [6], [7]; 4) quadruple gate (or GAA).”
FinFET design considerations based on 3-D simulation and analytical modeling (2002, methodology): “Most of the results reported on FinFET are based on experiments or 2-D simulation [ 14 ].”
A spacer patterning technology for nanoscale CMOS (2002, background): “Two promising structures are the ultrathin body (UTB) FET with a single gate [1] and the double-gate FinFET [2], [3].”
The Tunnel Source (PNPN) n-MOSFET: A Novel High Performance Transistor (2008, background): “engineering solutions such as improving the device architecture [1], [2], introducing materials into the channel region with superior transport properties (SiGe, Ge, etc.”
High-performance fully depleted silicon nanowire (diameter /spl les/ 5 nm) gate-all-around CMOS devices (2006, background): “Among the many innovative approaches, double-gated FinFET [3], [4], tri-gated [5], Π-gated [6], Ω-gated [7], nanowire body [8]–[11], and gateall-around (GAA) [12]–[14] MOSFETs have attracted much”