Complementary tunneling transistor for low power application

By Peng-Fei Wang, K. Hilsenbeck, T. Nirschl, M. Oswald, C. Stepper, M. Weis, D. Schmitt-Landsiedel, W. Hansch. 2004

489 citations recorded by the source corpus.

Subfields: Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/5c22382d350a880090f87f472885abb2f635a3d2

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In Electrical and Electronic Engineering

Citations in the corpus

Double-Gate Tunnel FET With High-$\kappa$ Gate Dielectric (2007, background): “For these simulations, the doping levels were 1 × 1020, 1 × 1017, and 5 × 1018 atoms/cm3 for the source, intrinsic, and drain regions, respectively.”
Low-Voltage Tunnel Transistors for Beyond CMOS Logic (2010, unknown): “TFET appeared in 2004 by Wang [ 4 ], Bhuwalka [5], and Appenzeller [6], but was certainly being considered in many groups.”
Effect of Pocket Doping and Annealing Schemes on the Source-Pocket Tunnel Field-Effect Transistor (2011, background): “Another factor affecting experimental TFETs, particularly Si-based TFETs, is ON-current levels several magnitudes lower in comparison to conventional MOSFETs [9], [18], [22].”
Tunnel field-effect transistors as energy-efficient electronic switches (2011, background): “However, by designing an asymmetry in the doping level or profile, or by restricting the movement of one type of charge carrier using heterostructures, the tunnelling barrier at the drain can be widened to suppress the ambipolarit”
Doping-Less Tunnel Field Effect Transistor: Design and Investigation (2013, background): “Abrupt junctions are essential for efficient tunneling in TFETs [1], [2], [7].”
Interfacial Charge Analysis of Heterogeneous Gate Dielectric-Gate All Around-Tunnel FET for Improved Device Reliability (2016, unknown): “2564448 (conduction in both the directions) [8].”
A Compact 2-D Analytical Model for Electrical Characteristics of Double-Gate Tunnel Field-Effect Transistors With a SiO2/High- $k$ Stacked Gate-Oxide Structure (2016, background): “where N1 = 1 × 1020 cm−3, N2 = 1 × 1016 cm−3, and N3 = 5 × 1018 cm−3 are assumed to be the doping concentrations of the source, channel and drain regions, respectively, to achieve a maximum ON-to-OFF current ratio [27] and the sign is taken negative for the source region and positive for the channel”
Low-subthreshold-swing tunnel transistors (2006, result): “Accordingly, the subthreshold swing in a tunnel transistor increases with gate–source voltage, a characteristic that has been observed in both measurements [5] and simulations [3], [4].”
Design of Tunneling Field-Effect Transistors Using Strained-Silicon/Strained-Germanium Type-II Staggered Heterojunctions (2008, background): “HERE has been a recent interest in the exploration of tunneling field-effect transistors (TFETs), where gatecontrolled band-to-band tunneling (BBT) is expected to reduce the subthreshold swing (SS) below the thermal limit of ln(10)kT /q per decade, enabling transistor operation at voltages below 0.5”
Steep Subthreshold Slope n- and p-Type Tunnel-FET Devices for Low-Power and Energy-Efficient Digital Circuits (2009, background): “T-FETs exhibit ambipolar behavior [13], [15].”
Design of U-Shape Channel Tunnel FETs With SiGe Source Regions (2014, background): “TUNNELING field-effect transistor (TFET) has become a promising candidate for future ultralow power devices [1], [2].”