Donghyuk Lee

Computer Networks and Communications · 2012–2017

A researcher in the Science corpus: 5 papers; trusts 10 researchers and is trusted by 4 researchers here, as inferred from the citation graph.

Subfields

• Computer Networks and Communications — 52 citations into it; #5,877 of 9,886 by trust here, #1,826 by citations
• Hardware and Architecture — 51 citations into it; #707 of 1,551 by trust here, #310 by citations
• Electrical and Electronic Engineering — 21 citations into it; #9,633 of 16,539 by trust here, #8,038 by citations
• Artificial Intelligence — 5 citations into it; #32,068 of 35,345 by trust here, #21,316 by citations

Whom Donghyuk Lee trusts overall

Their strongest outbound trust, strongest first, inferred from their citations.

1. Onur Mutlu
2. Yoongu Kim
3. Paul Rosenfeld
4. Vivek Seshadri
5. Chi-Keung Luk
6. Dean M. Tullsen
7. Moinuddin K. Qureshi
8. Thomas Moscibroda
9. Elliott Cooper-Balis
10. Jamie Liu

Who trusts Donghyuk Lee overall

1. Onur Mutlu
2. Vivek Seshadri
3. Yoongu Kim
4. Emre Kultursay
5. Jeremie S. Kim
6. Mahmut Taylan Kandemir
7. Saugata Ghose

Papers from Donghyuk Lee's perspective

Ordered by how strongly the researchers Donghyuk Lee trusts endorse each paper. Same corpus, a different order for every researcher.

1. Pin: building customized program analysis tools with dynamic instrumentation (ACM-SIGPLAN Symposium on Programming Language Design and Implementation)
2. Symbiotic jobscheduling for a simultaneous mutlithreading processor (SIGP)
3. Memory Performance Attacks: Denial of Memory Service in Multi-Core Systems (USENIX Security Symposium)
4. Space/time trade-offs in hash coding with allowable errors
5. Fair Queuing Memory Systems (Micro)
6. Memory access scheduling (Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat. No.RS00201))
7. Runahead execution: an alternative to very large instruction windows for out-of-order processors (The Ninth International Symposium on High-Performance Computer Architecture, 2003. HPCA-9 2003. Proceedings.)
8. Parallelism-Aware Batch Scheduling: Enhancing both Performance and Fairness of Shared DRAM Systems (International Symposium on Computer Architecture)
9. The gem5 simulator (CARN)
10. Self-Optimizing Memory Controllers: A Reinforcement Learning Approach (International Symposium on Computer Architecture)

Their papers

• Tiered-latency DRAM: A low latency and low cost DRAM architecture (2013) — 303 citations
• Flipping bits in memory without accessing them: An experimental study of DRAM disturbance errors (2014) — 712 citations
• Ambit: In-Memory Accelerator for Bulk Bitwise Operations Using Commodity DRAM Technology (2017) — 638 citations
• RowClone: Fast and energy-efficient in-DRAM bulk data copy and initialization (2013) — 491 citations
• A case for exploiting subarray-level parallelism (SALP) in DRAM (2012) — 415 citations