Jamie Liu

Hardware and Architecture · 2012–2013

A researcher in the Science corpus: 3 papers; trusts 8 researchers and is trusted by 8 researchers here, as inferred from the citation graph.

Subfields

• Hardware and Architecture — 35 citations into it; #377 of 1,551 by trust here, #420 by citations
• Computer Networks and Communications — 31 citations into it; #3,705 of 9,886 by trust here, #3,862 by citations
• Electrical and Electronic Engineering — 11 citations into it; #12,531 of 16,539 by trust here, #12,348 by citations

Whom Jamie Liu trusts overall

Their strongest outbound trust, strongest first, inferred from their citations.

1. Onur Mutlu
2. Paul Rosenfeld
3. Yoongu Kim
4. Chi-Keung Luk
5. Thomas Moscibroda
6. Dean M. Tullsen
7. Elliott Cooper-Balis
8. Dongsu Han
9. Bruce L. Jacob
10. Robert S. Cohn

Who trusts Jamie Liu overall

1. Onur Mutlu
2. Yoongu Kim
3. Emre Kultursay
4. Vivek Seshadri
5. Mahmut Taylan Kandemir
6. Jeremie S. Kim
7. Donghyuk Lee
8. Anand Sivasubramaniam
9. Yu Cai
10. Ross Daly

Papers from Jamie Liu's perspective

Ordered by how strongly the researchers Jamie Liu trusts endorse each paper. Same corpus, a different order for every researcher.

1. Pin: building customized program analysis tools with dynamic instrumentation (ACM-SIGPLAN Symposium on Programming Language Design and Implementation)
2. Symbiotic jobscheduling for a simultaneous mutlithreading processor (SIGP)
3. Memory Performance Attacks: Denial of Memory Service in Multi-Core Systems (USENIX Security Symposium)
4. Fair Queuing Memory Systems (Micro)
5. Parallelism-Aware Batch Scheduling: Enhancing both Performance and Fairness of Shared DRAM Systems (International Symposium on Computer Architecture)
6. Memory access scheduling (Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat. No.RS00201))
7. Runahead execution: an alternative to very large instruction windows for out-of-order processors (The Ninth International Symposium on High-Performance Computer Architecture, 2003. HPCA-9 2003. Proceedings.)
8. Space/time trade-offs in hash coding with allowable errors
9. Self-Optimizing Memory Controllers: A Reinforcement Learning Approach (International Symposium on Computer Architecture)
10. DRAMSim2: A Cycle Accurate Memory System Simulator (IEEE computer architecture letters)

Their papers

• Tiered-latency DRAM: A low latency and low cost DRAM architecture (2013) — 303 citations
• RAIDR: Retention-aware intelligent DRAM refresh (2012) — 545 citations
• A case for exploiting subarray-level parallelism (SALP) in DRAM (2012) — 415 citations