Thomas Moscibroda
Computer Networks and Communications · 2006–2013
A researcher in the Science corpus: 11 papers; trusts 39 researchers and is trusted by 27 researchers here, as inferred from the citation graph.
Subfields
- Computer Networks and Communications — 93 citations into it; #1,671 of 9,886 by trust here, #1,744 by citations
- Hardware and Architecture — 49 citations into it; #55 of 1,551 by trust here, #260 by citations
- Electrical and Electronic Engineering — 43 citations into it; #1,612 of 16,539 by trust here, #5,811 by citations
- Information Systems — 12 citations into it
- Software — 6 citations into it
Whom Thomas Moscibroda trusts overall
Their strongest outbound trust, strongest first, inferred from their citations.
- Chi-Keung Luk
- William (Bill) J. Dally
- Li-Shiuan Peh
- Onur Mutlu
- Timothy Sherwood
- Stijn Eyerman
- Rene L. Cruz
- Seongbeom Kim
- Dean M. Tullsen
- Changkyu Kim
Who trusts Thomas Moscibroda overall
- Onur Mutlu
- Yoongu Kim
- Rachata Ausavarungnirun
- Olga Goussevskaia
- Adwait Jog
- Sai Prashanth Muralidhara
- Saugata Ghose
- Emre Kultursay
- Mahmut Taylan Kandemir
- Jamie Liu
Papers from Thomas Moscibroda's perspective
Ordered by how strongly the researchers Thomas Moscibroda trusts endorse each paper. Same corpus, a different order for every researcher.
- Balancing thoughput and fairness in SMT processors (2001 IEEE International Symposium on Performance Analysis of Systems and Software. ISPASS.)
- Fair cache sharing and partitioning in a chip multiprocessor architecture (Proceedings. 13th International Conference on Parallel Architecture and Compilation Techniques, 2004. PACT 2004.)
- Ad hoc On-Demand Distance Vector (AODV) Routing (Request for Comments)
- An adaptive, non-uniform cache structure for wire-delay dominated on-chip caches (ASPLOS X)
- Symbiotic jobscheduling for a simultaneous mutlithreading processor (SIGP)
- A delay model and speculative architecture for pipelined routers (Proceedings HPCA Seventh International Symposium on High-Performance Computer Architecture)
- Flattened Butterfly Topology for On-Chip Networks (Micro)
- Automatically characterizing large scale program behavior (ASPLOS X)
- Pin: building customized program analysis tools with dynamic instrumentation (ACM-SIGPLAN Symposium on Programming Language Design and Implementation)
- Topology control of multihop wireless networks using transmit power adjustment (Proceedings IEEE INFOCOM 2000. Conference on Computer Communications. Nineteenth Annual Joint Conference of the IEEE Computer and Communications Societies (Cat. No.00CH37064))
Their papers
- A case for adapting channel width in wireless networks (2008) — 315 citations
- Allocating dynamic time-spectrum blocks in cognitive radio networks (2007) — 302 citations
- Stall-Time Fair Memory Access Scheduling for Chip Multiprocessors (2007) — 599 citations
- White space networking with wi-fi like connectivity (2009) — 470 citations
- Flikker: saving DRAM refresh-power through critical data partitioning (2011) — 472 citations
- The Complexity of Connectivity in Wireless Networks (2006) — 322 citations
- Walkie-Markie: Indoor Pathway Mapping Made Easy (2013) — 326 citations
- Reducing memory interference in multicore systems via application-aware memory channel partitioning (2011) — 298 citations
- A case for bufferless routing in on-chip networks (2009) — 459 citations
- Parallelism-Aware Batch Scheduling: Enhancing both Performance and Fairness of Shared DRAM Systems (2008) — 599 citations
- Memory Performance Attacks: Denial of Memory Service in Multi-Core Systems (2007) — 330 citations