Memory Performance Attacks: Denial of Memory Service in Multi-Core Systems

By Thomas Moscibroda, Onur Mutlu. USENIX Security Symposium, 2007

330 citations recorded by the source corpus.

View Paper: https://www.semanticscholar.org/paper/1b938edfde3b3b04c13599c2db87c72b7962f383

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Citations in the corpus

Eliminating the hypervisor attack surface for a more secure cloud (2011, background): “The memory controller and bus, on the other hand, do not in today’s processors [28].”
Memory scaling: A systems architecture perspective (2013, background): “Such uncontrolled interference can lead to denial of service to some applications [52], low system performance [57, 58], and an inability to satisfy performance requirements [57, 69, 22], which makes the system uncontrollable and unpredictable.”
Thread Cluster Memory Scheduling: Exploiting Differences in Memory Access Behavior (2010, background): “Thread-unaware scheduling policies have been shown to be low-performance and prone to starvation when multiple competing threads share the memory controller in general-purpose multicore/multithreaded systems [11, 16, 18, 4, 13, 14, 5].”
Enhancing lifetime and security of PCM-based Main Memory with Start-Gap Wear Leveling (2009, background): “Such an attack is more severe than Denial of Service (DoS) [14] in that memory resource (line) becomes permanently incapable of servicing future requests, whereas, in DoS attacks the resource is capable of – but unavailable for – service.”
Processing Data Where It Makes Sense: Enabling In-Memory Computation (2019, background): “, due to the ever-increasing need to process large amounts of data at real time, and predictable performance continues to be a critical concern in the design of modern computing systems [2, 16, 117, 118, 119, 120, 121, 122, 123], it is increasingly critical to design low-latency main memory chips.”
A case for exploiting subarray-level parallelism (SALP) in DRAM (2012, background): “As a result, requests of an application that could have otherwise hit in the row-buffer will miss in the row-buffer, signiﬁcantly degrading the performance of the application (and potentially the overall system) [37, 40, 56, 67].”
OWL: cooperative thread array aware scheduling techniques for improving GPGPU performance (2013, background): “This problem also becomes more severe with core scaling and the increase in the number of simultaneously executing threads [24], in a way that is similar to the memory bandwidth problem in multi-core systems [38, 42].”
Reducing memory interference in multicore systems via application-aware memory channel partitioning (2011, background): “Reducing Memory Interference in Multicore Systems via Application-Aware Memory Channel Partitioning Sai Prashanth Muralidhara Lavanya Subramanian Onur Mutlu Pennsylvania State University Carnegie Mellon University Carnegie Mellon University smuralid@cse.psu.edu lsubrama@ece.cmu.edu onur@cmu.edu M”
MASK: Redesigning the GPU Memory Hierarchy to Support Multi-Application Concurrency (2018, background): “The Silver Queue allows the GPU to (1) avoid starvation when one or more applications hog memory bandwidth, and (2) improve fairness when multiple applications execute concurrently [15, 84].”
Stall-Time Fair Memory Access Scheduling for Chip Multiprocessors (2007, unknown): “Our previous work [20] describes how the unfairness in the DRAM subsystem can be exploited by malicious programs to perform denial of service against other programs sharing the memory system.”
ATLAS: A scalable and high-performance scheduling algorithm for multiple memory controllers (2010, background): “By prioritizing rowhit requests, it aims to maximize DRAM throughput, but as shown in previous work [35, 36, 32] this thread-unaware policy leads to low system throughput and starvation of threads with low row-buffer locality.”
Fairness via source throttling: a configurable and high-performance fairness substrate for multi-core memory systems (2010, unknown): “1) a baseline system with no fairness techniques employed in the shared memory system, using LRU cache replacement and FR-FCFS memory scheduling [27], both of which have been shown to be unfair [15, 21, 24].”
Parallelism-Aware Batch Scheduling: Enhancing both Performance and Fairness of Shared DRAM Systems (2008, background): “starve requests/threads for long time periods, causing unf airness and relatively low overall system throughput [28, 22, 25].”
RAIDR: Retention-aware intelligent DRAM refresh (2012, background): “This unintuitive result occurs because while the common FR-FCFS memory scheduling policy maximizes memory throughput, it does not necessarily maximize system performance; applications with high row hit rates can starve applications with low row hit rates [34, 35].”
A survey of microarchitectural timing attacks and countermeasures on contemporary hardware (2016, background): “Thus, a subset of the cores, working together, can saturate the system memory controllers, ﬁlling internal buses, therefore dramatically increasing the latency of memory loads and stores for all processes [117].”