A case for exploiting subarray-level parallelism (SALP) in DRAM

By Yoongu Kim, Vivek Seshadri, Donghyuk Lee, Jamie Liu, Onur Mutlu. International Symposium on Computer Architecture, 2012

415 citations recorded by the source corpus.

Modern DRAMs have multiple banks to serve multiple memory requests in parallel. However, when two requests go to the same bank, they have to be served serially, exacerbating the high latency of off-chip memory. Adding more banks to the system to mitigate this problem incurs high system cost. Our goal in this work is to achieve the benefits of increasing the number of banks with a low cost approach. To this end, we propose three new mechanisms that overlap the latencies of different requests that go to the same bank. The key observation exploited by our mechanisms is that a modern DRAM bank is implemented as a collection of subarrays that operate largely independently while sharing few global peripheral structures. Our proposed mechanisms (SALP-1, SALP-2, and MASA) mitigate the negative impact of bank serialization by overlapping different components of the bank access latencies of multiple requests that go to different subarrays within the same bank. SALP-1 requires no changes to the existing DRAM structure and only needs reinterpretation of some DRAM timing parameters. SALP-2 and MASA require only modest changes (<;0.15% area overhead) to the DRAM peripheral structures, which are much less design constrained than the DRAM core. Evaluations show that all our schemes significantly improve performance for both single-core systems and multi-core systems. Our schemes also interact positively with application-aware memory request scheduling in multi-core systems.

Subfields: Computer Networks and Communications, Hardware and Architecture

View Paper: https://www.semanticscholar.org/paper/cc0b01c2b52af296cf6b2e0cd001c5c50156bde8

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Citations in the corpus

Flipping bits in memory without accessing them: An experimental study of DRAM disturbance errors (2014, methodology): “the cells — and immediately writes the charge back into the cells [38, 41, 43].”
Ambit: In-Memory Accelerator for Bulk Bitwise Operations Using Commodity DRAM Technology (2017, methodology): “, number of banks or subarrays [59]).”
TRRespass: Exploiting the Many Sides of Target Row Refresh (2020, methodology): “We refer the reader to prior work [18]–[21], [29], [30], [50], [51], [57]–[61], [67], [68], [82]–[85], [97] for a more detailed description of DRAM organization and operation.”
Ramulator: A Fast and Extensible DRAM Simulator (2016, background): “Academic SBA/SSA (2010) [38]; Staged Reads (2012) [8]; RAIDR (2012) [27]; SALP (2012) [24]; TL-DRAM (2013) [26]; RowClone (2013) [37]; Half-DRAM (2014) [39]; Row-Buffer Decoupling (2014) [33]; SARP (2014) [6]; AL-DRAM (2015) [25]”
RowClone: Fast and energy-efficient in-DRAM bulk data copy and initialization (2013, methodology): “Figure 3: Steps involved in accessing a cache line from a subarray (figure adapted from [31])”
Processing Data Where It Makes Sense: Enabling In-Memory Computation (2019, background): “Unfortunately, it has become increasingly difficult in recent years to scale all of these dimensions [1, 2, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31], and the main memory bottleneck has instead been worsening.”
Evaluating STT-RAM as an energy-efficient main memory alternative (2013, methodology): “DRAM operation is described in more detail in [25], [28], [31], [45].”
DRISA: A DRAM-based Reconfigurable In-Situ Accelerator (2017, background): “Previous work [54] shows such modification incurs ignorable area overhead.”
Tiered-latency DRAM: A low latency and low cost DRAM architecture (2013, background): “[24] propose schemes to parallelize accesses to diUerent subarrays within a bank, thereby overlapping their latencies.”