Fair Queuing Memory Systems

By Kyle J. Nesbit, Nidhi Aggarwal, James Laudon, James E. Smith. Micro, 2006

351 citations recorded by the source corpus.

Subfields: Computer Networks and Communications, Hardware and Architecture

View Paper: https://www.semanticscholar.org/paper/23f4f3430cd97f034563dc0a41039c5fbc58f6a3

How researchers see this paper

The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.

In Computer Networks and Communications

In Hardware and Architecture

Citations in the corpus

Heracles: Improving resource efficiency at scale (2015, background): “Despite significant research on memory bandwidth isolation [30, 56, 32, 59], there are no hardware isolation mechanisms in commercially available chips.”
Cooperative Caching for Chip Multiprocessors (2006, methodology): “Here we focus on the impact of destructive interference occurring in the last-level CMP caches, assuming a fair memory system as proposed in [114].”
Bubble-up: Increasing utilization in modern warehouse scale computers via sensible co-locations (2011, background): “One direction that has attracted much research attention is the management of shared cache and bandwidth through techniques such as resource partitioning [4, 20, 27–34, 38] , throttling [ 7 ] and adaptive cache replacement policies [ 14 ].”
Thread Cluster Memory Scheduling: Exploiting Differences in Memory Access Behavior (2010, methodology): “Fair queueing memory schedulers [16, 18] adapted variants of the fair queueing algorithm from computer networks”
Reducing memory interference in multicore systems via application-aware memory channel partitioning (2011, background): “…Carnegie Mellon University smuralid@cse.psu.edu lsubrama@ece.cmu.edu onur@cmu.edu Mahmut Kandemir Thomas Moscibroda Pennsylvania State University Microsoft Research Asia kandemir@cse.psu.edu moscitho@microsoft.com ABSTRACT Main memory is a major shared resource among cores in a multicore system.”
Self-Optimizing Memory Controllers: A Reinforcement Learning Approach (2008, methodology): “To understand whether the speedups delivered by our RL-based memory controller could also be achieved by simply addressing any potential fairness problems across threads, we evaluate Nesbit et al.’s Fair Queueing scheduler [31].”
Memory Performance Attacks: Denial of Memory Service in Multi-Core Systems (2007, methodology): “As shown in [22], however, this algorithm can have negative effects on fairness in chip-multiprocessor s ystems.”
ATLAS: A scalable and high-performance scheduling algorithm for multiple memory controllers (2010, methodology): “Since each bank acts independently in FQM, FQM does not require coordination across controllers, but this comes at the expense of relatively low system performance.”
Parallelism-Aware Batch Scheduling: Enhancing both Performance and Fairness of Shared DRAM Systems (2008, methodology): “[28] applied Network Fair-Queueing (NFQ) techniques to DRAM contr llers in order to divide the DRAM bandwidth among multiple threads sharing the DRAM system.”
Fairness via source throttling: a configurable and high-performance fairness substrate for multi-core memory systems (2010, neutral): “We refer to this baseline as NoFairness, 2) a system with only fair cache capacity management using the virtual private caches technique [25], called FairCache, 3) a system with a network fair queuing (NFQ) fair memory scheduler [24] combined with fair cache capacity management [25], called NFQ+Fair”
MemGuard: Memory bandwidth reservation system for efficient performance isolation in multi-core platforms (2013, methodology): “Such effects are typical in COTS systems due to the characteristics of modern DRAM controllers [16]: (1) each DRAM chip is composed of multiple resources, called banks, which can be accessed in parallel.”
A case for exploiting subarray-level parallelism (SALP) in DRAM (2012, background): “, [6, 16, 23, 24, 38, 40, 41, 43]) that prioritize certain favorable requests in the memory controller to improve system performance and/or fairness.”
Stall-Time Fair Memory Access Scheduling for Chip Multiprocessors (2007, methodology): “19This bandwidth partitioning is performed dynamically by adjusting a thread’s virtual deadlines inverse-proportionally to its share [22].”