Memory access scheduling

By Scott Rixner, William (Bill) J. Dally, U. Kapasi, Peter R. Mattson, John Douglas Owens. Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat. No.RS00201), 2000

1,051 citations recorded by the source corpus.

The bandwidth and latency of a memory system are strongly dependent on the manner in which accesses interact with the "3-D" structure of banks, rows, and columns characteristic of contemporary DRAM chips. There is nearly an order of magnitude difference in bandwidth between successive references to different columns within a row and different rows within a bank. This paper introduces memory access scheduling, a technique that improves the performance of a memory system by reordering memory references to exploit locality within the 3-D memory structure. Conservative reordering, in which the first ready reference in a sequence is performed, improves bandwidth by 40% for traces from five media benchmarks. Aggressive reordering, in which operations are scheduled to optimize memory bandwidth, improves bandwidth by 93% for the same set of applications. Memory access scheduling is particularly important for media processors where it enables the processor to make the most efficient use of scarce memory bandwidth.

Subfields: Computer Networks and Communications, Hardware and Architecture

View Paper: https://www.semanticscholar.org/paper/e1e9537b1dffb1d49a389733e60fcf630e5f36f6

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Citations in the corpus

Analyzing CUDA workloads using a detailed GPU simulator (2009, methodology): “Performance is reduced by over 40% when using FIFO for BFS, LIB, MUM, RAY, and WP.”
Page placement in hybrid memory systems (2011, background): “For example, to improve access throughput, the MC may choose to buffer particular requests (e.g., LLC write-backs) and/or reorder requests according to the system’s current state [3, 17, 30].”
ATLAS: A scalable and high-performance scheduling algorithm for multiple memory controllers (2010, background): “Analysis Several observations are in order from the above results: First, as expected, FCFS and FR-FCFS policies, which are thread-unaware and prone to starvation, perform significantly worse than PAR-BS and ATLAS, which are thread-aware, starvation-free, and aimed to optimize system performance.”
MASK: Redesigning the GPU Memory Hierarchy to Support Multi-Application Concurrency (2018, methodology): “Within both the Silver Queue and Normal Queue , FR-FCFS [110, 152] is used to schedule requests.”
Memory Performance Attacks: Denial of Memory Service in Multi-Core Systems (2007, background): “Interested readers can ﬁnd more details in [29, 8, 37].”
Self-Optimizing Memory Controllers: A Reinforcement Learning Approach (2008, methodology): “Rixner et al. [37] show that none of the ﬁxed policies studied provide the best performance for all workloads and under all circumstances.”
Tiered-latency DRAM: A low latency and low cost DRAM architecture (2013, neutral): “Memory 64/64-entry read/write request queue, Controller row-interleaved mapping, closed-page policy, FR-FCFS scheduling [41]”
Accel-Sim: An Extensible Simulation Framework for Validated GPU Modeling (2018, background): “Figure 9 shows the sensitivity of memory-intensive GPGPU workloads for two memory scheduling policies: the na¨ıve ﬁrst-come ﬁrst-serve scheduling (FCFS) and the advanced out-of-order First-row-ready ﬁrst-come ﬁrst-serve scheduling (FR FCFS) [58].”
Ambit: In-Memory Accelerator for Bulk Bitwise Operations Using Commodity DRAM Technology (2017, background): “Memory Controller 8 KB row size, FR-FCFS [94, 118] scheduling”
Domain-specific Genetic Algorithm for Multi-tenant DNNAccelerator Scheduling (2021, methodology): “For job prioritizing, heuristics such as FCFS, SJF and others have been dound to be effective [3, 5, 45, 61, 86].”
Fairness via source throttling: a configurable and high-performance fairness substrate for multi-core memory systems (2010, neutral): “6.6 GHz out of order processor, 15 stages, Decode/retire up to 4 instructions Execution Core Issue/execute up to 8 micro instructions 256-entry reorder buffer Fetch up to 2 branches; 4K-entry BTB Front End 64K-entry Hybrid branch predictor L1 I-cache: 32KB, 4-way, 2-cycle, 64B line L1 D-cache: 32K”
RAIDR: Retention-aware intelligent DRAM refresh (2012, background): “Memory controller FR-FCFS scheduling [41, 54], line-interleaved mapping, open-page policy”
Parallelism-Aware Batch Scheduling: Enhancing both Performance and Fairness of Shared DRAM Systems (2008, methodology): “For single-threaded systems, the FR-FCFS policy was shown to pr ovide the best average performance [33, 32], significantly better than the simpler FCFS policy, which simply schedules all requests ac cording to their arrival order, regardless of the row-buffer state.”
Ramulator: A Fast and Extensible DRAM Simulator (2016, neutral): “5Single rank, 800Mhz, 11-11-11, row-interleaved, FR-FCFS [35], open-row policy.”
3D-Stacked Memory Architectures for Multi-core Processors (2008, background): “We assume a memory controller implementation that attempts to schedule accesses to the same row together to increase row buffer hit rates [36].”
Stall-Time Fair Memory Access Scheduling for Chip Multiprocessors (2007, neutral): “Instead, they try to maximize the data throughput obtained from the DRAM using a ﬁrst-ready ﬁrst-come-ﬁrst-serve (FR-FCFS) policy [25, 24].”