Parallelism-Aware Batch Scheduling: Enhancing both Performance and Fairness of Shared DRAM Systems

By Onur Mutlu, Thomas Moscibroda. International Symposium on Computer Architecture, 2008

599 citations recorded by the source corpus.

Subfields: Computer Networks and Communications, Hardware and Architecture

View Paper: https://www.semanticscholar.org/paper/434fa04db769935ae61bbcf4d9faa602b9a8c730

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Citations in the corpus

Fairness via source throttling: a configurable and high-performance fairness substrate for multi-core memory systems (2010, unknown): “2% compared respectively to a system with no fairness techniques employed and a system with stateof-the-art fairness mechanisms implemented for both shared cache capacity [25] and the shared memory controller [23].”
Evaluating STT-RAM as an energy-efficient main memory alternative (2013, background): “Further, data accesses originating from different cores can interleave in any fashion which can cause the memory row buffer locality to degrade [4], [43], [46], [65].”
OWL: cooperative thread array aware scheduling techniques for improving GPGPU performance (2013, methodology): “Bank level parallelism (BLP) is defined as the number of average memory banks that are accessed when there is at least one outstanding memory request at any of the banks [26, 27, 41, 42].”
Thread Cluster Memory Scheduling: Exploiting Differences in Memory Access Behavior (2010, methodology): “Grouping of threads into clusters happens in a synchronized manner across all memory controllers to better exploit bank-level parallelism [5, 14].”
Memory scaling: A systems architecture perspective (2013, methodology): “To achieve these goals, we have designed various solutions including QoS-aware memory controllers [57, 58, 53, 32, 33, 54, 5, 69, 41, 23], interconnects [17, 18, 27, 28, 13, 59, 60, 19], and entire memory systems including caches, interconnect, and memory [22, 24, 19].”
MASK: Redesigning the GPU Memory Hierarchy to Support Multi-Application Concurrency (2018, methodology): “We report performance using weighted speedup [42, 43], a commonly-used metric to evaluate the performance of a multi-application workload [15, 38, 39, 68, 71, 72, 86, 88, 89, 124, 125, 132].”
Tiered-latency DRAM: A low latency and low cost DRAM architecture (2013, background): “[4, 9, 23, 22, 32, 31]), to mitigate inter-application interference and queueing latencies in multi-core systems.”
Reducing memory interference in multicore systems via application-aware memory channel partitioning (2011, methodology): “Weighted Speedup 15 10 5 1.2 FRFCFS FCFS 1.15 PARBS 0 % of memory-intensive benchmarks in a workload Figure 7: MCP and IMPS performance across memoryintensity categories.”
Processing Data Where It Makes Sense: Enabling In-Memory Computation (2019, background): “, due to the ever-increasing need to process large amounts of data at real time, and predictable performance continues to be a critical concern in the design of modern computing systems [2, 16, 117, 118, 119, 120, 121, 122, 123], it is increasingly critical to design low-latency main memory chips.”
Memory power management via dynamic voltage/frequency scaling (2011, background): “As is shown, memory bandwidth is highly variable, and depends on many factors: memory access rate, LLC residency, memory-and bank-level parallelism (MLP [13] and BLP [28]) and the ability to tolerate memory latency, for example.”
ATLAS: A scalable and high-performance scheduling algorithm for multiple memory controllers (2010, methodology): “Other scheduling algorithms [35, 36] provide higher system throughput and are configurable, but they require significant coordination to achieve these benefits when implemented in a multiple-memorycontroller system.”
A case for exploiting subarray-level parallelism (SALP) in DRAM (2012, background): “This is referred to as bank-level parallelism [24, 41].”
Error Characterization, Mitigation, and Recovery in Flash-Memory-Based Solid-State Drives (2017, background): “, DRAM banks [84], [85], [99], [101], [102], [108], [193]–[196]), the planes can execute flash operations in parallel, but the planes within a die share a single set of data and control buses [185].”