Yoongu Kim
Computer Networks and Communications · 2010–2016
A researcher in the Science corpus: 8 papers; trusts 22 researchers and is trusted by 16 researchers here, as inferred from the citation graph.
Subfields
- Computer Networks and Communications — 74 citations into it; #1,800 of 9,886 by trust here, #943 by citations
- Hardware and Architecture — 74 citations into it; #173 of 1,551 by trust here, #164 by citations
- Electrical and Electronic Engineering — 20 citations into it; #5,117 of 16,539 by trust here, #6,143 by citations
- Information Systems — 17 citations into it
Whom Yoongu Kim trusts overall
Their strongest outbound trust, strongest first, inferred from their citations.
- Onur Mutlu
- Thomas Moscibroda
- Scott Rixner
- Dean M. Tullsen
- Engin Ipek
- Paul Rosenfeld
- Chi-Keung Luk
- Stijn Eyerman
- Jamie Liu
- Yossi Matias
Who trusts Yoongu Kim overall
- Onur Mutlu
- Vivek Seshadri
- Rachata Ausavarungnirun
- Daniel Gruss
- Donghyuk Lee
- Saugata Ghose
- Sai Prashanth Muralidhara
- Jamie Liu
- Amirali Boroumand
- Emre Kultursay
Papers from Yoongu Kim's perspective
Ordered by how strongly the researchers Yoongu Kim trusts endorse each paper. Same corpus, a different order for every researcher.
- Balancing thoughput and fairness in SMT processors (2001 IEEE International Symposium on Performance Analysis of Systems and Software. ISPASS.)
- Pin: building customized program analysis tools with dynamic instrumentation (ACM-SIGPLAN Symposium on Programming Language Design and Implementation)
- Memory access scheduling (Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat. No.RS00201))
- Symbiotic jobscheduling for a simultaneous mutlithreading processor (SIGP)
- Fair Queuing Memory Systems (Micro)
- Memory Performance Attacks: Denial of Memory Service in Multi-Core Systems (USENIX Security Symposium)
- Space/time trade-offs in hash coding with allowable errors
- Parallelism-Aware Batch Scheduling: Enhancing both Performance and Fairness of Shared DRAM Systems (International Symposium on Computer Architecture)
- ImageNet classification with deep convolutional neural networks
- Deep Residual Learning for Image Recognition (Computer Vision and Pattern Recognition)
Their papers
- Ramulator: A Fast and Extensible DRAM Simulator (2016) — 781 citations
- Tiered-latency DRAM: A low latency and low cost DRAM architecture (2013) — 303 citations
- Flipping bits in memory without accessing them: An experimental study of DRAM disturbance errors (2014) — 712 citations
- Memory Systems (2014) — 195 citations
- RowClone: Fast and energy-efficient in-DRAM bulk data copy and initialization (2013) — 491 citations
- A case for exploiting subarray-level parallelism (SALP) in DRAM (2012) — 415 citations
- ATLAS: A scalable and high-performance scheduling algorithm for multiple memory controllers (2010) — 461 citations
- Thread Cluster Memory Scheduling: Exploiting Differences in Memory Access Behavior (2010) — 445 citations