Moinuddin K. Qureshi

Hardware and Architecture · 2006–2018

A researcher in the Science corpus: 7 papers; trusts 12 researchers and is trusted by 29 researchers here, as inferred from the citation graph.

Subfields

• Hardware and Architecture — 30 citations into it; #91 of 1,551 by trust here, #205 by citations
• Computer Networks and Communications — 29 citations into it; #1,115 of 9,886 by trust here, #1,322 by citations
• Artificial Intelligence — 6 citations into it; #19,343 of 35,345 by trust here, #31,361 by citations
• Atomic and Molecular Physics, and Optics — 6 citations into it

Whom Moinuddin K. Qureshi trusts overall

Their strongest outbound trust, strongest first, inferred from their citations.

1. Erez Perelman
2. Seongbeom Kim
3. Greg Hamerly
4. John Preskill
5. Onur Mutlu
6. Daniel N. Lynch
7. Alfred J. Menezes
8. Peter J. Denning
9. Dhruba Chandra
10. Timothy Sherwood

Who trusts Moinuddin K. Qureshi overall

1. Yuejian Xie
2. Jichuan Chang
3. Onur Mutlu
4. Vivek Seshadri
5. Gabriel H. Loh
6. G. Sohi
7. Ripal Nathuji
8. Sergey Zhuravlev
9. Yoongu Kim
10. Jason Mars

Papers from Moinuddin K. Qureshi's perspective

Ordered by how strongly the researchers Moinuddin K. Qureshi trusts endorse each paper. Same corpus, a different order for every researcher.

1. Fair cache sharing and partitioning in a chip multiprocessor architecture (Proceedings. 13th International Conference on Parallel Architecture and Compilation Techniques, 2004. PACT 2004.)
2. Balancing thoughput and fairness in SMT processors (2001 IEEE International Symposium on Performance Analysis of Systems and Software. ISPASS.)
3. Symbiotic jobscheduling for a simultaneous mutlithreading processor (SIGP)
4. A first-order superscalar processor model (Proceedings. 31st Annual International Symposium on Computer Architecture, 2004.)
5. Runahead execution: an alternative to very large instruction windows for out-of-order processors (The Ninth International Symposium on High-Performance Computer Architecture, 2003. HPCA-9 2003. Proceedings.)
6. Amdahl's Law in the Multicore Era (Computer)
7. A Case for MLP-Aware Cache Replacement (International Symposium on Computer Architecture)
8. Using SimPoint for accurate and efficient simulation (Measurement and Modeling of Computer Systems)
9. Checkpoint processing and recovery: towards scalable large instruction window processors (Proceedings. 36th Annual IEEE/ACM International Symposium on Microarchitecture, 2003. MICRO-36.)
10. Speculative lock elision: enabling highly concurrent multithreaded execution (Proceedings. 34th ACM/IEEE International Symposium on Microarchitecture. MICRO-34)

Their papers

• Enhancing lifetime and security of PCM-based Main Memory with Start-Gap Wear Leveling (2009) — 759 citations
• Not All Qubits Are Created Equal: A Case for Variability-Aware Policies for NISQ-Era Quantum Computers (2018) — 446 citations
• Accelerating critical section execution with asymmetric multi-core architectures (2009) — 320 citations
• Adaptive insertion policies for managing shared caches (2008) — 327 citations
• Adaptive insertion policies for high performance caching (2007) — 760 citations
• Utility-Based Cache Partitioning: A Low-Overhead, High-Performance, Runtime Mechanism to Partition Shared Caches (2006) — 1,094 citations
• A Case for MLP-Aware Cache Replacement (2006) — 337 citations