The gem5 simulator

By N. Binkert, Bradford M. Beckmann, Gabriel Black, Steven K. Reinhardt, A. Saidi, Arkaprava Basu, Joel Hestness, Derek Hower, Tushar Krishna, S. Sardashti and 6 more. CARN, 2011

5,271 citations recorded by the source corpus.

Subfields: Computer Networks and Communications, Hardware and Architecture

View Paper: https://www.semanticscholar.org/paper/ce6bae7429f6e2ee34e92b09fdbff7a909ccd84f

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Citations in the corpus

Overcoming the challenges of crossbar resistive memory architectures (2015, methodology): “Simulation Setup We use GEM5 [2] as our simulation platform with the integration of NVMain [32], which is a cycleaccurate memory simulator for both DRAM and non-volatile memories.”
Processing Data Where It Makes Sense: Enabling In-Memory Computation (2019, background): “, gem5 [216], zsim [217], gem5-gpu [218], GPGPUSim [219]) to provide a robust environment that can evaluate how various PIM architectures affect the entire compute stack, and can allow designers to identify memory, workload, and system characteristics that affect the efficiency of PIM execution.”
A detailed and flexible cycle-accurate Network-on-Chip simulator (2013, methodology): “Additionally , BookSim2 offers an interface that can be integrated with the GEM5 [15] full-system simulator, replacing Garnet [14] or the simple network model included with GEM5.”
Efficient virtual memory for big memory servers (2013, background): “Actually, a single simulation point using the gem5 simulator [10] would take several weeks to months and at least twice as much physical memory as the actual workload.”
An Evaluation of High-Level Mechanistic Core Models (2014, methodology): “2011] or the atomic (synchronous) memory access mode in gem5 [Binkert et al. 2011] complete the simulation of each memory access in a single function call, updating all structures (e.”
Learning Performance-Improving Code Edits (2023, methodology): “To address this challenge, we measure program performance using the gem5 (Binkert et al., 2011) full system simulator, which provides detailed microarchitectural emulation of modern processors.”
A Survey of Mobile Device Virtualization (2016, background): “Moreover, several ARM instruction set emulators also exist, such as Qemu [Bellard 2005] and gem5 [Binkert et al. 2011].”
Ambit: In-Memory Accelerator for Bulk Bitwise Operations Using Commodity DRAM Technology (2017, methodology): “We evaluate the bene � ts of Ambit on real-world applications using the Gem5 full-system simulator [22].”
DRAMsim3: A Cycle-Accurate, Thermal-Capable DRAM Simulator (2020, positive): “DRAMsim3 can be integrated into popular CPU simulators or simulation frameworks such as SST [13], ZSim [15] and Gem5 [1] as their memory backend simulator.”
OuterSPACE: An Outer Product Based Sparse Matrix Multiplication Accelerator (2018, methodology): “To evaluate the performance of the outer product algorithm on OuterSPACE, we modeled the key elements, namely, the PEs, the cache-crossbar hierarchy and the HBM, using the gem5 simulator [13].”
ZSim: fast and accurate microarchitectural simulation of thousand-core systems (2013, methodology): “Emulation is the natural choice when the simulated ISA is diﬀerent from the host’s, and many simulators choose it to be portable. gem5 [4, 5, 25], Flexus [51] and MARSS [29] are current representative emulation-based systems.”
The gem5 Simulator: Version 20.0+ (2020, background): “Basic functionality existed in the original gem5 release [19], but major improvements have been made in the 50 By Gabriel Black 51 by Brandon Potter past few years.”
InvisiSpec: Making Speculative Execution Invisible in the Cache Hierarchy (2018, methodology): “[33] N. Binkert, B. Beckmann, G. Black, S. K. Reinhardt, A. Saidi, A. Basu, J. Hestness, D. R. Hower, T. Krishna, S. Sardashti, R. Sen, K. Sewell, M. Shoaib, N. Vaish, M. D. Hill, and D. A. Wood, “The Gem5 Simulator,” ACM SIGARCH Computer Architecture News, 2011.”
A study of mobile device utilization (2015, background): “Mobybench [7] is also comprised of popular applications, which has already been ported to the gem5 simulator [22].”
Ramulator: A Fast and Extensible DRAM Simulator (2016, background): “Ramulator is available in two different formats: one for standalone usage and the other for integrated usage with gem5 [4].”
Google Workloads for Consumer Devices: Mitigating Data Movement Bottlenecks (2018, methodology): “We evaluate our proposed PIM architectures using the gem5 [10] full-system simulator.”
NDA: Near-DRAM acceleration architecture leveraging commodity DRAM devices and standard memory modules (2015, methodology): “4 Simulation Platform We extended the gem5 simulator [57] with the ARM ISA to support CGRA execution, 3D-stacked memory, and nontemporal memory accesses.”