RowClone: Fast and energy-efficient in-DRAM bulk data copy and initialization

By Vivek Seshadri, Yoongu Kim, Chris Fallin, Donghyuk Lee, Rachata Ausavarungnirun, Gennady Pekhimenko, Yixin Luo, Onur Mutlu, Phillip B. Gibbons, Michael A. Kozuch and 1 more. Micro, 2013

491 citations recorded by the source corpus.

Several system-level operations trigger bulk data copy or initialization. Even though these bulk data operations do not require any computation, current systems transfer a large quantity of data back and forth on the memory channel to perform such operations. As a result, bulk data operations consume high latency, bandwidth, and energy — degrading both system performance and energy efficiency. In this work, we propose RowClone, a new and simple mechanism to perform bulk copy and initialization completely within DRAM — eliminating the need to transfer any data over the memory channel to perform such operations. Our key observation is that DRAM can internally and efficiently transfer a large quantity of data (multiple KBs) between a row of DRAM cells and the associated row buffer. Based on this, our primary mechanism can quickly copy an entire row of data from a source row to a destination row by first copying the data from the source row to the row buffer and then from the row buffer to the destination row, via two back-to-back activate commands. This mechanism, which we call the Fast Parallel Mode of RowClone, reduces the latency and energy consumption of a 4KB bulk copy operation by 11.6× and 74.4×, respectively, and a 4KB bulk zeroing operation by 6.0× and 41.5×, respectively. To efficiently copy data between rows that do not share a row buffer, we propose a second mode of RowClone, the Pipelined Serial Mode, which uses the shared internal bus of a DRAM chip to quickly copy data between two banks. RowClone requires only a 0.01% increase in DRAM chip area. We quantitatively evaluate the benefits of RowClone by focusing on fork, one of the frequently invoked system calls, and five other copy and initialization intensive applications. Our results show that RowClone can significantly improve both single-core and multi-core system performance, while also significantly reducing main memory bandwidth and energy consumption.

Subfields: Computer Networks and Communications, Hardware and Architecture

View Paper: https://www.semanticscholar.org/paper/8f8f2b1beaa33be4f7ed14a5884c2333bcccf640

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Citations in the corpus

RowHammer: A Retrospective (2019, unknown): “, [13]–[15], [18], [22], [24], [34]–[36], [56], [63], [72], [77], [78], [80], [91], [92], [95], [96], [99], [101], [102], [111], [121]–[123], [151], [153], [154], [160], [161], [172], [178], [179], [182], [195], [198], [215]–[219], [221], [222], [228], [257], and [260]).”
Ambit: In-Memory Accelerator for Bulk Bitwise Operations Using Commodity DRAM Technology (2017, methodology): “RowClone [97] e � ciently performs bulk copy and initialization inside DRAM.”
PRIME: A Novel Processing-in-Memory Architecture for Neural Network Computation in ReRAM-Based Main Memory (2016, unknown): “Like prior work [77], the inter-bank data movement is implemented by exploiting the internal data bus shared by all the banks in a chip.”
Processing Data Where It Makes Sense: Enabling In-Memory Computation (2019, methodology): “There are a number of example PIM architectures that make use of this approach [31, 82, 83, 84, 85, 86, 92, 93].”
A scalable processing-in-memory accelerator for parallel graph processing (2015, background): “In this context, it is critical to examine specialized PIM systems for important domains of applications [2, 48, 53, 62, 63].”
Profiling a warehouse-scale computer (2015, background): “The plot is a cumulative histogram of measured DRAM band-width across a sufﬁciently large number of machines.”
DRISA: A DRAM-based Reconfigurable In-Situ Accelerator (2017, methodology): “Rowclone [81] has supported in-DRAM row-to-row copy with minor modification on existing DRAMs.”
TRRespass: Exploiting the Many Sides of Target Row Refresh (2020, methodology): “We refer the reader to prior work [18]–[21], [29], [30], [50], [51], [57]–[61], [67], [68], [82]–[85], [97] for a more detailed description of DRAM organization and operation.”
Compute Caches (2017, background): “Past processing-in-memory (PIM) solutions proposed to move processing logic near the cache [4], [5] or main memory [6], [7].”