Tiered-latency DRAM: A low latency and low cost DRAM architecture

By Donghyuk Lee, Yoongu Kim, Vivek Seshadri, Jamie Liu, Lavanya Subramanian, Onur Mutlu. International Symposium on High-Performance Computer Architecture, 2013

303 citations recorded by the source corpus.

The capacity and cost-per-bit of DRAM have historically scaled to satisfy the needs of increasingly large and complex computer systems. However, DRAM latency has remained almost constant, making memory latency the performance bottleneck in today's systems. We observe that the high access latency is not intrinsic to DRAM, but a trade-off made to decrease cost-per-bit. To mitigate the high area overhead of DRAM sensing structures, commodity DRAMs connect many DRAM cells to each sense-amplifier through a wire called a bitline. These bitlines have a high parasitic capacitance due to their long length, and this bitline capacitance is the dominant source of DRAM latency. Specialized low-latency DRAMs use shorter bitlines with fewer cells, but have a higher cost-per-bit due to greater sense-amplifier area overhead. In this work, we introduce Tiered-Latency DRAM (TL-DRAM), which achieves both low latency and low cost-per-bit. In TL-DRAM, each long bitline is split into two shorter segments by an isolation transistor, allowing one segment to be accessed with the latency of a short-bitline DRAM without incurring high cost-per-bit. We propose mechanisms that use the low-latency segment as a hardware-managed or software-managed cache. Evaluations show that our proposed mechanisms improve both performance and energy-efficiency for both single-core and multi-programmed workloads.

Subfields: Electrical and Electronic Engineering, Hardware and Architecture

View Paper: https://www.semanticscholar.org/paper/762733e27c86698d1300a0666a30cd704505c709

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Citations in the corpus

RowClone: Fast and energy-efficient in-DRAM bulk data copy and initialization (2013, methodology): “A recent prior work, TL-DRAM [34], uses this observation to move data between two segments within the same subarray.”
Ambit: In-Memory Accelerator for Bulk Bitwise Operations Using Commodity DRAM Technology (2017, methodology): “Similar to some prior works [67, 68, 97], Ambit requires faulty rows to be mapped to spare rows within the same subarray.”
Flipping bits in memory without accessing them: An experimental study of DRAM disturbance errors (2014, background): “Project Zero demonstrated in 2015 that RowHammer can be effectively exploited by user-level programs to gain kernel privileges on real systems [42, 43].”
Processing Data Where It Makes Sense: Enabling In-Memory Computation (2019, background): “The trend is even worse for memory bandwidth per core – in the last 20 years, DRAM chip capacity (for the most commonDDRx chip of the time) has improved around 128× while DRAM bandwidth has increased only around 20× [22, 23, 31].”
Memory scaling: A systems architecture perspective (2013, methodology): “We have recently shown that we can architect a heterogeneous-latency bitline DRAM, called Tiered-Latency DRAM (TL-DRAM) [42], by dividing a long bitline into two shorter segments using an isolation transistor: a low-latency segment can be accessed with the latency and efficiency of a shortbitline DR”
Evaluating STT-RAM as an energy-efficient main memory alternative (2013, methodology): “DRAM operation is described in more detail in [25], [28], [31], [45].”
RowHammer: A Retrospective (2019, background): “These works provide examples of how an intelligent memory controller can alleviate the retention failures, and thus the DRAM refresh problem [158], [159], as well as the DRAM latency problem [145], [146].”
Ramulator: A Fast and Extensible DRAM Simulator (2016, unknown): “Academic SBA/SSA (2010) [38]; Staged Reads (2012) [8]; RAIDR (2012) [27]; SALP (2012) [24]; TL-DRAM (2013) [26]; RowClone (2013) [37]; Half-DRAM (2014) [39]; Row-Buffer Decoupling (2014) [33]; SARP (2014) [6]; AL-DRAM (2015) [25]”